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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) August inventions list 08/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/25/2011 > patent applications in patent subcategories. inventions list
20110208946 - Dual mode floating point multiply accumulate unit: Disclosed are various embodiments of a stream processing unit for single instruction multiple data (SIMD) processing, wherein the stream processing unit executes a stage of a Multiply-Accumulate calculation. In one embodiment, the stream processing unit comprises a plurality of scalar arithmetic logic units (ALUs) configured to receive data having a... Agent: Via Technologies, Inc.
20110208947 - System and method for simplifying transmission in parallel computing system: Simplifying transmission in a distributed parallel computing system. The method includes: identifying at least one item in a data input to the parallel computing unit; creating a correspondence relation between the at least one item and indices thereof according to a simplification coding algorithm, where the average size of the... Agent: International Business Machines Corporation
20110208948 - Reading to and writing from peripherals with temporally separated redundant processor execution: Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others.... Agent: Infineon Technologies Ag
20110208949 - Hardware thread disable with status indicating safe shared resource condition: A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor... Agent: International Business Machines Corporation
20110208950 - Processes, circuits, devices, and systems for scoreboard and other processor improvements: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the... Agent: Texas Instruments Incorporated
20110208951 - Instruction processor and method therefor: A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register... Agent: Advanced Micro Devices, Inc.
20110208952 - Programmable controller for executing a plurality of independent sequence programs in parallel: A programmable controller which executes a plurality of independent sequence programs in parallel is provided with an ASIC, including a plurality of arithmetic-logic units and a plurality of arbitration circuits, and MPUs as many as the arbitration circuits. The entire execution time of the programmable controller is shortened by changing... Agent: Fanuc Corporation08/18/2011 > patent applications in patent subcategories. inventions list
20110202745 - Method and apparatus for computing massive spatio-temporal correlations using a hybrid cpu-gpu approach: A CPU may select a variable from a variable set as a dependent variable. The variable set may be part of the data structure that includes a plurality of vector values, a vector value associated with a variable set of n number of variables, and each variable of the variable... Agent: International Business Machines Corporation
20110202746 - Processing architecture: The invention is directed towards a processing apparatus for a portable communication device. The apparatus includes: a central processing unit, first and second digital signal processing units, a first dual port memory unit adapted to store data shared between the central processing unit and the first digital signal processing unit,... Agent: St-ericsson Sa
20110202747 - Instruction length based cracking for instruction of variable length storage operands: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on... Agent: International Business Machines Corporation
20110202748 - Load pair disjoint facility and instruction therefore: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs.... Agent: International Business Machines Corporation
20110202749 - Instruction compressing apparatus and method: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle... Agent: Samsung Electronics Co., Ltd.08/11/2011 > patent applications in patent subcategories. inventions list
20110197047 - Method for forming a parallel processing system: A definition file included in the present invention includes a plurality of parallel descriptions that respectively define a plurality of parallel processes performed independently. The plurality of parallel descriptions include a first parallel description showing a first parallel process with a plurality of data inputs including at least one data... Agent: Fuji Xerox Co., Ltd.
20110197048 - Dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamically reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware... Agent:
20110197049 - Two pass test case generation using self-modifying instruction replacement: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the... Agent: International Business Machines Corporation
20110197050 - Wait instruction: A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait state associated with a plurality of predefined wait state exit conditions. The device is configured to load into an electronic... Agent:08/04/2011 > patent applications in patent subcategories. inventions list
20110191567 - Relating to single instruction multiple data (simd) architectures: Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of... Agent:
20110191568 - Information processing apparatus and method of controlling the same: An information processing apparatus is provided. The apparatus includes a communication unit configured to communicate with another apparatus, a main processing unit capable of controlling communication processing by the communication unit and other processing, a communication processing unit capable of controlling the communication processing by the communication unit and a... Agent: Canon Kabushiki Kaisha
20110191569 - Data processing device and semiconductor integrated circuit device: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is... Agent:
20110191570 - Method and apparatus for performing logical compare operations: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on... Agent:Previous industry: Electrical computers and digital processing systems: memory
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