|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
07/2011 | Recent | 14: | | | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) July category listing 07/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/28/2011 > patent applications in patent subcategories. category listing
20110185151 - Data processing architecture: A parallel processor is described which is operated in a SIMD manner. The processor comprises: a plurality of processing elements connected in a string and grouped into a plurality of processing units, wherein each processing unit comprises a plurality of processing elements which each have direct interconnections with all of... Agent:
20110185150 - Low-overhead misalignment and reformatting support for simd: Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization... Agent: Sun Microsystems, Inc.
20110185152 - Reconfigurable circuit and semiconductor integrated circuit: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the... Agent: Fujitsu Semiconductor Limited
20110185153 - Simultaneous execution resumption of multiple processor cores after core state information dump to facilitate debugging via multi-core processor simulator using the state information: A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the... Agent: Via Technologies, Inc.
20110185154 - Synchronization of multiple processor cores: The invention relates to a spinlock-based multi-core synchronization technique in a real-time environment, wherein multiple processor cores perform spinning attempts to request a lock and the lock is allocated to at most one of the multiple cores for a mutually exclusive operation thereof. A method embodiment of the technique comprises... Agent: Elektrobit Automotive Software Gmbh
20110185155 - Microprocessor that performs fast repeat string loads: A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a cache memory of the microprocessor a series of cache lines implicated by a string of data bytes specified by the instruction. A memory... Agent: Via Technologies, Inc.
20110185156 - Executing watchpoint events for debugging in a \"break before make\" manner: A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with... Agent: Lsi Corporation
20110185157 - Multifunction hexadecimal instruction form system and program product: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point... Agent: International Business Machines Corporation
20110185158 - History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered... Agent: International Business Machines Corporation
20110185159 - Processor including age tracking of issue queue instructions: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age... Agent: International Business Machines Corporation
20110185160 - Multi-core processor with external instruction execution rate heartbeat: A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of... Agent: Via Technologies, Inc.07/21/2011 > patent applications in patent subcategories. category listing
20110179251 - Power saving asynchronous computer: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent:
20110179252 - method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores... Agent: Qst Holdings, LLC
20110179253 - Efficient multi-core processing of events: A computer implemented method for handling events in a multi-core processing environment is provided. The method comprises handling an event by a second application running on a second core, in response to determining that the event is initiated by a first application running on a first core; and running a... Agent: International Business Machines Corporation
20110179254 - Limiting speculative instruction fetching in a processor: The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching... Agent: Sun Microsystems, Inc.
20110179255 - Data processing reset operations: A processor 4 is provided with reset circuitry 48 which generates a reset signal to reset a plurality of state parameters. Partial reset circuitry 50 is additionally provided to reset a proper subset of this plurality of state parameters. The reset circuitry triggers a redirection of program flow. The partial... Agent: Arm Limited
20110179256 - processing bypass directory tracking system and method: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to... Agent:
20110179257 - Image forming device, image forming method and computer readable medium: A data processing device including a reception unit, an instruction unit and a storage unit. The reception unit receives instructions for processing at a processing execution device. The instruction unit instructs the processing execution device to cancel a power saving state of the processing execution device and execute the processing... Agent: Fuji Xerox Co., Ltd.
20110179258 - Precise data return handling in speculative processors: The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned... Agent: Sun Microsystems, Inc.07/14/2011 > patent applications in patent subcategories. category listing
20110173413 - Embedding global barrier and collective in a torus network: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set... Agent: International Business Machines Corporation
20110173414 - Maximized memory throughput on parallel processing devices: In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus processing may take relatively small amounts of time to compute as compared to memory accesses times required to read the stream and write the results. Therefore, memory throughput... Agent: Nvidia Corporation
20110173416 - Data processing device and parallel processing unit: A data processing device in which parallel processing elements can efficiently perform processing is provided. A parallel processing module includes plural processing elements, banks A and B provided to correspond to the processing elements and used to store data to be used when the processing elements perform processing, and an... Agent: Renesas Electronics Corporation
20110173415 - Multi-core system and data transfer method: According to one embodiment, each of routers includes: a cache mechanism that stores data transferred to the other routers or processor elements; and a unit that reads out, when an access generated from each of the processor elements is transferred thereto, if target data of the access is stored in... Agent: Kabushiki Kaisha Toshiba
20110173417 - Programming idiom accelerators: A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an... Agent:
20110173418 - Instruction set extension using 3-byte escape opcode: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the... Agent:
20110173419 - Look-ahead wake-and-go engine with speculative execution: A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. If a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the... Agent:
20110173420 - Processor resume unit: A system for enhancing performance of a computer includes a computer system having a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processor. An external unit is external to the processor for monitoring specified... Agent: International Business Machines Corporation
20110173421 - Multi-input and binary reproducible, high bandwidth floating point adder in a collective network: To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers.... Agent: International Business Machines Corporation
20110173422 - Pause processor hardware thread until pin: A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A... Agent: International Business Machines Corporation
20110173423 - Look-ahead hardware wake-and-go mechanism: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the... Agent:07/07/2011 > patent applications in patent subcategories. category listing
20110167240 - Method of rotating data in a plurality of processing elements: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to... Agent: Micron Technology, Inc.
20110167241 - Superconducting circuit for high-speed lookup table: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory... Agent: Hypres, Inc.
20110167242 - Multiple instruction execution mode resource-constrained device: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of... Agent: Oracle America, Inc.
20110167243 - Space-efficient mechanism to support additional scouting in a processor using checkpoints: Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were... Agent:
20110167244 - Early instruction text based operand store compare reject avoidance: A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction... Agent: International Business Machines Corporation
20110167245 - Task list generation, parallelism templates, and memory management for multi-core systems: There is provided a multi-core system that provides automated task list generation, parallelism templates, and memory management. By constructing, profiling, and analyzing a sequential list of functions to be executed in a parallel fashion, corresponding parallel execution templates may be stored for future lookup in a database. A processor may... Agent: Mindspeed Technologies, Inc.
20110167246 - Systems and methods for data detection including dynamic scaling: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding... Agent: Lsi Corporation
20110167247 - System for efficiently tracing data in a data processing system: A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not... Agent: Arm Limited
20110167248 - Efficient resumption of co-routines on a linear stack: Unsuspended co-routines are handled by the machine call stack mechanism in which the stack grows and shrinks as recursive calls are made and returned from. When a co-routine is suspended, however, additional call stack processing is performed. A suspension message is issued, and the entire resume-able part of the call... Agent: Microsoft CorporationPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150122:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.28995 seconds