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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) June invention type 06/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/30/2011 > patent applications in patent subcategories. invention type
20110161623 - Data parallel function call for determining if called routine is data parallel: Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor,... Agent: International Business Machines Corporation
20110161624 - Floating point collect and operate: Mechanisms are provided for performing a floating point collect and operate for a summation across a vector for a dot product operation. A routing network placed before the single instruction multiple data (SIMD) unit allows the SIMD unit to perform a summation across a vector with a single stage of... Agent: International Business Machines Corporation
20110161625 - Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor: A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each dimension of a G×H matrix of nodes, where G≧N and H≧N and N is a positive odd integer. Also,... Agent:
20110161626 - Routing packets in on-chip networks: Techniques for packet routing in an on-chip network are provided. In one embodiment, a method for routing packets in a multi-core processor including multiple cores connected by an on-chip network includes identifying ports that are incorrect while routing the packet. After receiving the packet at an input port, some of... Agent: Empire Technology Development LLC
20110161627 - Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection: An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and... Agent:
20110161628 - Data processing apparatus and method of controlling reconfigurable circuit layer: According to one embodiment, a data processing apparatus includes plural reconfigurable circuit layers, a first memory, a selecting unit, and a configuring unit. In each of the plural reconfigurable circuit layers, a processing circuit can be reconfigured. The first memory stores circuit information representing processing circuits that should be configured.... Agent: Toshiba Tec Kabushiki Kaisha
20110161629 - Arithmetic processor, information processor, and pipeline control method of arithmetic processor: An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a registration unit into which an aborted instruction is registered, the aborted instruction being the first instruction when the first... Agent: Fujitsu Limited
20110161630 - General purpose hardware to replace faulty core components that may also provide additional processor functionality: An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to... Agent:
20110161631 - Arithmetic processing unit, information processing device, and control method: According to an aspect of an embodiment of the invention, an arithmetic processing unit includes a first cache memory unit that holds a part of data stored in a storage device; an address register that holds an address; a flag register that stores flag information; and a decoder that decodes... Agent: Fujitsu Limited
20110161632 - Compiler assisted low power and high performance load handling: A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to... Agent:
20110161634 - Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system: A processor includes a buffer that separates a sequence of instructions having no operand into segments and stores the segments, a data holder that holds data to be processed, a decoder that references the data and sequentially decodes at least one of the instructions from the top of the sequence,... Agent: Sony Corporation
20110161633 - Systems and methods for monitoring out of order data decoding: Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the... Agent: Lsi Corporation
20110161637 - Apparatus and method for parallel processing: An apparatus and method for parallel processing in consideration of degree of parallelism are provided. One of a task parallelism and a data parallelism is dynamically selected while a job is processed. In response to a task parallelism being selected, a sequential version code is allocated to a core or... Agent: Samsung Electronics Co., Ltd.
20110161636 - Method of managing power of multi-core processor, recording medium storing program for performing the same, and multi-core processor system: Provided are a method of managing power of a multi-core processor, a recording medium storing a program for performing the method, and a multi-core processor system. The method of managing power of a multi-core processor having at least one core includes determining a parallel-processing section on the basis of information... Agent: Postech Academy - Industry Foundation
20110161635 - Rotate instructions that complete execution without reading carry flag: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution... Agent:
20110161638 - Ising systems: helical band geometry for dtc and integration of dtc into a universal quantum computational protocol: Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to implement a logical gate T, anyonic state teleportation into and out of the topology altering structure, and certain geometries of the (1,−2)-bands, a classical... Agent: Microsoft Corporation
20110161639 - Event counter checkpointing and restoring: A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods... Agent:
20110161640 - Apparatus and method for configurable processing: A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, the or each module being connectable to receive input operands indicated in an instruction, and a programmable lookup... Agent:
20110161641 - Spe software instruction cache: An application thread executes a direct branch instruction that is stored in an instruction cache line. Upon execution, the direct branch instruction branches to a branch descriptor that is also stored in the instruction cache line. The branch descriptor includes a trampoline branch instruction and a target instruction space address.... Agent: International Business Machines Corporation
20110161642 - Parallel execution unit that extracts data parallelism at runtime: Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the... Agent: International Business Machines Corporation
20110161643 - Runtime extraction of data parallelism: Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further... Agent: International Business Machines Corporation06/23/2011 > patent applications in patent subcategories. invention type
20110153980 - Multi-stage reconfiguration device and reconfiguration method, logic circuit correction device, and reconfigurable multi-stage logic circuit: To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector... Agent: Kyushu Institute Of Technology
20110153981 - Heterogeneous computer architecture based on partial reconfiguration: Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same... Agent:
20110153982 - Systems and methods for collecting data from multiple core processors: Systems and methods are disclosed for collecting data from cores of a multi-core processor using collection packets. A collection packet can traverse through cores of the multi-core processor while accumulating requested data. Upon completing the accumulation of the requested data from all required cores, the collection packet can be transmitted... Agent: Bbn Technologies Corp.
20110153983 - Gathering and scattering multiple data elements: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution... Agent:
20110153984 - Dynamic voltage change for multi-core processing: Embodiments of the disclosure generally set forth techniques for supplying different voltage levels and clock signals to a processor core. One example method includes determining a first workload of a first processor core in the multi-core processor for performing a first computing task associated with a first image area and... Agent:
20110153985 - Systems and methods for queue level ssl card mapping to multi-core packet engine: The present invention is directed towards systems and methods for distributed operation of a plurality of cryptographic cards in a multi-core system. In various embodiments, a plurality of cryptographic cards providing encryption/decryption resources are assigned to a plurality of packet processing engines in operation on a multi-core processing system. One... Agent:
20110153986 - Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is... Agent: International Business Machines Corporation
20110153988 - Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments: Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments are disclosed herein. An example pre-fetch unit for use with a pre-fetch operation includes a first size function executed by a processor to determine a size of an object associated with a pre-fetch operation; a comparator to compare... Agent:
20110153987 - Reverse simultaneous multi-threading: A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system... Agent: International Business Machines Corporation
20110153989 - Synchronizing simd vectors: A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by... Agent:
20110153990 - System, apparatus, and method for supporting condition codes: An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality... Agent:
20110153991 - Dual issuing of complex instruction set instructions: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue... Agent: International Business Machines Corporation
20110153992 - Methods and apparatus to manage object locks: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass... Agent:
20110153993 - Add instructions to add three source operands: A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The... Agent:
20110153995 - Arithmetic apparatus including multiplication and accumulation, and dsp structure and filtering method using the same: Disclosed are an arithmetic apparatus including MAC calculation, and a DSP structure and a filtering method using the same. The arithmetic apparatus includes: first and second registers storing one or more pieces of n-bit data (n is a natural number); a third register storing one or more pieces of 2n... Agent: Electronics And Telecommunications Research Institute
20110153994 - Multiplication instruction for which execution completes without writing a carry flag: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of... Agent:
20110153996 - Parallel and vectored gilbert-johnson-keerthi graphics processing: Parallel and vectored data structures may be used in a single instruction multiple data processor that applies the Gilbert-Johnson-Keerthi algorithm. As a result, the performance of multi-core processors doing graphics processing may be increased in some cases.... Agent:
20110153997 - Bit range isolation instructions, methods, and apparatus: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value... Agent:
20110153998 - Methods and apparatus for attaching application specific functions within an array processor: A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters... Agent: Altera Corporation
20110154000 - Adaptive optimized compare-exchange operation: A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.... Agent:
20110153999 - Methods and apparatus to manage partial-commit checkpoints with fixup support: Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the... Agent:
20110154001 - System and method for processing interrupts in a computing system: A system, processor and method are provided for digital signal processing A processor may initiate processing a sequence of instructions followed by an interrupt Each instruction may be processed in respective sequential pipeline slots A branch detector may detect or determine if an instruction is a branch instruction, for example,... Agent:
20110154002 - Methods and apparatuses for efficient load processing using buffers: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store... Agent:06/16/2011 > patent applications in patent subcategories. invention type
20110145543 - Execution of variable width vector processing instructions: A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing... Agent: Sun Microsystems, Inc.
20110145544 - Multi-level hierarchical routing matrices for pattern-recognition processors: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition... Agent: Micron Technology, Inc.
20110145545 - Computer-implemented method of processing resource management: A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first... Agent: International Business Machines Corporation
20110145546 - Deferred page clearing in a multiprocessor computer system: Processing within a multiprocessor computer system is facilitated by: logically clearing a data page by setting, in association with invalidate page table entry or set storage key processing, a page initialize bit for the data page to a clear data value without physically clearing data from the data page; and... Agent: International Business Machines Corporation
20110145547 - Reconfigurable elements: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.... Agent:
20110145548 - Microprocessor for executing byte compiled java code: A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel.... Agent: Atmel Corporation
20110145549 - Pipelined decoding apparatus and method based on parallel processing: An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra... Agent: Electronics And Telecommunications Research Institute
20110145550 - Non-quiescing key setting facility: A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of... Agent: International Business Machines Corporation
20110145551 - Two-stage commit (tsc) region for dynamic binary optimization in x86: Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more... Agent:
20110145552 - Handling operating system (os) transitions in an unbounded transactional memory (utm) mode: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the... Agent:
20110145553 - Accelerating parallel transactions using cache resident transactions: Handling parallelism in transactions. One embodiment includes a method that includes beginning a cache resident transaction. The method further includes encountering a nested structured parallelism construct within the cache resident transaction. A determination is made as to whether the transaction would run faster serially in cache resident mode or faster... Agent: Microsoft Corporation
20110145554 - Data processing device with adjustable performance level and method of operating such device: A data processing device has a processor (10) operable at selectable ones of a plurality of performance levels. The processor generates a workload data vector indicating a workload of the processor as a function of time. A memory stores a set of reference workload vectors. A pattern matcher (18) detects... Agent: Nxp B.v.06/09/2011 > patent applications in patent subcategories. invention type
20110138151 - Processing elements, mixed mode parallel processor system, processing method by processing elements, mixed mode parallel processor method, processing program by processing elements and mixed mode parallel processing program: Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the... Agent: Nec Corporation
20110138152 - Instruction control device: A processor which executes threads having different characteristics is provided with an instruction control device. In the instruction control device, a first instruction control unit issues an instruction included in a first instruction sequence to an instruction execution unit. In addition, a second instruction control unit issues an instruction included... Agent: Panasonic Corporation
20110138153 - Mechanism for selecting instructions for execution in a multithreaded processor: In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given... Agent:
20110138154 - Optimization of a computing environment in which data management operations are performed: Described are embodiments of an invention for optimizing a computing environment that performs data management operations such as encryption, deduplication and compression. The computing environment includes data components and a management system. The data components operate on data during the lifecycle of the data. The management system identifies all the... Agent: International Business Machines Corporation
20110138155 - Vector computer and instruction control method therefor: A vector computer executing vector operations via vector pipeline processing is restructured to dynamically perform an overtaking control on vector gather/scatter instructions. Minimum/maximum values among vector elements of vector registers are determined based on the result of fixed-point calculation defining an address dependency source instruction in accordance with a vector... Agent:
20110138156 - Method and apparatus for evaluating a logical expression and processor making use of same: A method and associated processor suitable for executing machine instructions for evaluating a logical expression are provided. The approach suggested makes use of a memory and an extended set of instructions. The memory, which can be embodied in a general purpose register for example, is for storing information related to... Agent:
20110138157 - Convolution computation for many-core processor architectures: A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of... Agent: Synopsys, Inc.
20110138158 - Integrated circuit: The present invention allows an integrated circuit to easily control interfaces utilizing new interface types. In order to achieve the above, an ASIC (100) includes: a microprocessor (110) which executes a predetermined instruction code and (an instruction code for a configuration); and a functional block (130) which generates, through an... Agent:06/02/2011 > patent applications in patent subcategories. invention type
20110131391 - Integrated circuit with stacked computational units and configurable through vias: A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the... Agent: International Business Machines Corporation
20110131392 - Method and apparatus for scalable and super-scalable information processing using binary gate circuits structured by code-selected pass transistors: A processing space comprises an array of transistors empowered by forming connections through circuit pass transistors to power and data input/output means and connections therebetween through signal pass transistors. By structuring the needed circuits at the site(s) of the data the von Neumann bottleneck is eliminated, which increases the computing... Agent:
20110131393 - Programmable processor architecture: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than... Agent: 3plus1 Technology, Inc.
20110131394 - Apparatus and method for using branch prediction heuristics for determination of trace formation readiness: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality... Agent: International Business Machines Corporation
20110131396 - Timing analysis: One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to... Agent: Xmos Limited
20110131397 - Multiprocessor system and multiprocessor control method: A multiprocessor system includes a memory that stores a program; an address notification register; a first processor; and a second processor, in which the first processor stores address information indicating an address from which the program is executed in the address notification register, when the first processor notifies an interrupt... Agent: Nec Electronics CorporationPrevious industry: Electrical computers and digital processing systems: memory
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