|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) May archived by USPTO category 05/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/26/2011 > patent applications in patent subcategories. archived by USPTO category
20110125984 - Microprocessor: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied... Agent:
20110125985 - Providing a dedicated communication path separate from a second path to enable communication between compliant sequencers using an assertion signal: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves... Agent:
20110125986 - Reducing inter-task latency in a multiprocessor system: A method of reducing inter-task latency for software comprising a sequence of instructions including a synchronous remote procedure call to be executed on a multiprocessor system comprising a calling processor and at least one remote engine. The method comprises the steps of: inputting the software; inputting a runtime resource description... Agent: Arm Limited
20110125987 - Dedicated arithmetic decoding instruction: A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.... Agent: Qualcomm Incorporated
20110125988 - Arithmetic processing unit: In an arithmetic processing unit adopting register windows, a configuration is made such that the reading process of a register file is controlled by two stages of a current window selection and a register selection, and the register selected at a plurality of reading ports of the register is set... Agent: Fujitsu Limited05/19/2011 > patent applications in patent subcategories. archived by USPTO category
20110119467 - Massively parallel, smart memory based accelerator: Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to... Agent: Nec Laboratories America, Inc.
20110119469 - Balancing workload in a multiprocessor system responsive to programmable adjustments in a syncronization instruction: In a multiprocessor system with threads running in parallel, workload balancing is facilitated by recognizing a plurality of levels of sub-tasks of a memory synchronization instruction and selectively choosing for at least one thread to do less than all of levels of these sub-tasks in response to the memory synchronization... Agent: International Business Machines Corporation
20110119468 - Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator: A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality... Agent: International Business Machines Corporation
20110119470 - Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses: In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting... Agent: International Business Machines Corporation
20110119471 - Method and apparatus to extract integer and fractional components from floating-point data: A method is presented including decomposing a first value into many parts. Decomposing includes shifting (310) a rounded integer portion of the first value to generate a second value. Generating (320) a third value. Extracting (330) a plurality of significand bits from the second value to generate a fourth value.... Agent:
20110119472 - Branch predicting device, branch predicting method thereof, compiler, compiling method thereof, and medium for storing branch predicting program: A branch prediction mechanism 1000 within an information processing device 100 comprises a call stack 113 where function arguments are stacked when function calls are performed. The call stack 113 stores arguments relating to branch instructions within the function. The branch prediction mechanism 1000 stores the branch instruction address, the... Agent:05/12/2011 > patent applications in patent subcategories. archived by USPTO category
20110113217 - Generate predictes instruction for processing vectors: The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a first input vector, a second input vector, and optionally receiving a predicate vector (each of which includes N elements) as inputs. The processor then executes the vector instruction. Executing the vector instruction causes... Agent: Apple Inc.
20110113218 - Cross flow parallel processing method and system: Provided is a cross flow parallel processing method and system that may process multiple data flows and increase a parallel processing rate in a multi-processor that processes multiple cross data flows.... Agent: Electronics And Telecommunications Research Institute
20110113219 - Computer architecture for a mobile communication platform: A system includes first and second processors, first and second graphics processing units (GPUs), one or more peripheral devices, a switch matrix, and processor-readable memory. The switch matrix comprises programmable data paths between the processors, the GPUs, and the peripheral devices. Software encoded in the process-readable memory includes a first... Agent: Sunman Engineering, Inc.
20110113221 - Data sharing in chip multi-processor systems: System, computer readable medium and method for providing transparent access to shared data (16) in a chip multi-processor system (900), without using locks or transactional memory constructs, where a first set of processing entities (12) communicate with a second set of processing entities (14) via a task queue (20) for... Agent: Telefonaktiebolaget L M Ericsson (publ)
20110113220 - Multiprocessor: The multiprocessor includes: a first processor allocating a different register file to each of a predetermined number of threads to be executed from among plural threads, and executing the predetermined number of threads in parallel; and a second processor performing processing according to a processing request made by the first... Agent:
20110113222 - Method and apparatus for assigning thread priority in a processor or the like: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier... Agent: Intel Corporation
20110113223 - Branch target buffer for emulation environments: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a... Agent: International Business Machines Corporation
20110113224 - Execution time estimation method, execution time estimation program, and execution time estimation device: An execution time estimation device includes a program partitioning section that extracts partial programs partitioned by a conditional branch instruction or a function call instruction from a target program, a partial program execution time estimation calculating section that calculates the execution time of each of the partial programs to associate... Agent: Tokyo Institute Of Technology05/05/2011 > patent applications in patent subcategories. archived by USPTO category
20110107058 - Processor memory system: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid... Agent:
20110107059 - Multilayer parallel processing apparatus and method: A multilayer parallel processing apparatus. The multilayer parallel processing apparatus includes two or more hierarchical parallel processing units, each configured to process flow data corresponding to a hierarchy that is allocated thereto in response to inputting pieces of flow data configured with two or more hierarchies, and a common database... Agent: Electronics And Telecommunications Research Institute
20110107060 - Transposing array data on simd multi-core processor architectures: Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may comprise a SIMD conversion of a matrix M in a conventional data format. A mapping may be defined from each... Agent: International Business Machines Corporation
20110107061 - Performance of first and second macros while data is moving through hardware pipeline: A hardware pipeline has a number of rows including a first row, a last row, and an intermediate row between the first row and the last row. Each row stores a number of bytes of data as the data moves through the pipeline on a row-by-row basis from the first... Agent:
20110107062 - Interrupt handling: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal... Agent:
20110107063 - Vector processing apparatus and method: There is provided a vector processing apparatus and method allowing for the parallel processing of a plurality of different instructions while maintaining vector processing architecture. The vector processing apparatus includes an instruction memory storing a multiple instruction group including one or more instructions; an instruction fetch unit reading the multiple... Agent: Electronics And Telecommunications Research Institute
20110107064 - Data processor: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of... Agent: Renesas Electronics Corporation
20110107066 - Cascaded accelerator functions: Accelerator functions are cascaded, such that a result of one accelerator function is directly forwarded to another accelerator function, bypassing the processor requesting the functions to be performed. The cascading may be provided during compilation of a program specifying the functions to be performed, but can be dynamically reversed during... Agent: International Business Machines Corporation
20110107065 - Interconnect controller for a data processing device and method therefor: A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the... Agent: Freescale Semiconductor, Inc.
20110107067 - Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of... Agent: Elbrus International
20110107068 - Eliminating redundant operations for common properties using shared real registers: One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a... Agent: International Business Machines Corporation
20110107069 - Processor architecture for executing wide transform slice instructions: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Microunity Systems Engineering, Inc.
20110107070 - Patching of a read-only memory: An information processing device comprises a memory carrying a program, and a processor capable of executing the program. The program instructs the processor to determine whether a selected identifier is contained in a set of identifiers, and, if the processor has determined that the identifier is contained in the set... Agent:
20110107071 - System and method for using a branch mis-prediction buffer: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch... Agent:Previous industry: Electrical computers and digital processing systems: memory
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