Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) March listing by industry category 03/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
03/31/2011 > patent applications in patent subcategories.

20110078411 - Dynamically modifying program execution capacity: Techniques are described for managing program execution capacity, such as for a group of computing nodes that are provided for executing one or more programs for a user. In some situations, dynamic program execution capacity modifications for a computing node group that is in use may be performed periodically or... Agent:

20110078410 - Efficient pipelining of rdma for communications: Disclosed are a method of and system for multiple party communications in a processing system including multiple processing subsystems. Each of the processing subsystems includes a central processing unit and one or more network adapters for connecting said each processing subsystem to the other processing subsystems. A multitude of nodes... Agent: International Business Machines Corporation

20110078412 - Processor core stacking for efficient collaboration: A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core... Agent: International Business Machines Corporation

20110078413 - Arithmetic processing unit, semiconductor integrated circuit, and arithmetic processing method: An arithmetic processing apparatus includes an arithmetic circuit; a first memory configured to store data to be processed in the arithmetic circuit; a second memory configured to be accessed through a first path by the arithmetic circuit; a preloader configured to preload the data from the second memory into the... Agent: Fujitsu Limited

20110078415 - Efficient predicated execution for parallel processors: The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates... Agent:

20110078414 - Multiported register file for multithreaded processors and processors employing register windows: A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands... Agent:

20110078416 - Apparatus and method for control processing in dual path processor: A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit... Agent: Icera Inc.

20110078417 - Cooperative thread array reduction and scan operations: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan... Agent:

20110078419 - Set program parameter instruction: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data... Agent: International Business Machines Corporation

20110078418 - Support for non-local returns in parallel thread simd engine: One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method... Agent:

20110078420 - Method for adapting and executing a computer program and computer architecture therefore: A computer architecture (100) and a method for adapting and executing (200) a computer program therefore, is provided. A value is computed by processing the instructions comprised in a basic block of the program in accordance with a first mathematical function (208). An instruction comprising an original address is modified,... Agent: Nxp B.v.

20110078421 - Enhanced monitor facility: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an... Agent: International Business Machines Corporation

20110078422 - Image processing device having a plurality of control units: An image processing device includes an operating unit and a plurality of control units each configured to control the operating unit in order to execute a function on image data. The plurality of control units include at least a first control unit and a second control unit. When a first... Agent: Brother Kogyo Kabushiki Kaisha

20110078423 - Implementation of variable length instruction encoding using alias addressing: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second... Agent:

20110078424 - Optimizing program code using branch elimination: A method for optimizing program code is provided. The method comprises detecting a branch instruction comprising a condition expression, wherein the branch instruction, when executed by a processor, causes the processor to execute either a first set of instructions or a second set of instructions according to a value of... Agent: International Business Machines Corporation

20110078425 - Branch prediction mechanism for predicting indirect branch targets: A multithreaded microprocessor includes an instruction fetch unit that may fetch and maintain a plurality of instructions belonging to one or more threads and one or more execution units that may concurrently execute the one or more threads. The instruction fetch unit includes a target branch prediction unit that may... Agent:

20110078426 - Systems and methods for scenario-based process modeling: Methods and systems for scenario-based process modeling are described. In one example embodiment, a system for scenario-based process modeling can include a scenario module, a deviations module, a parallel tasks module, and a workflow generation engine. The scenario module is to receive a series of tasks to define a standard... Agent: Sap Ag

20110078427 - Trap handler architecture for a parallel processing unit: A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code... Agent:

03/24/2011 > patent applications in patent subcategories.

20110072236 - Method for efficient and parallel color space conversion in a programmable processor: The present invention relates to an efficient implementation of color space conversion in a SIMD processor as part of converting output of video decompression to interface to a display unit.... Agent:

20110072237 - Methods and apparatus for efficiently sharing memory and processing in a multi-processor: A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands... Agent:

20110072238 - Method for variable length opcode mapping in a vliw processor: The present invention provides a method for reducing program memory size required for a dual-issue processor with a scalar processor plus a SIMD vector processor. Coding the map of next group of instruction pairs in a no-operation (NOP) instruction of scalar and vector processor reduces the cases where one of... Agent:

20110072239 - Data multicasting in a distributed processor system: Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the... Agent: Board Of Regents, University Of Texas System

20110072240 - Self-similar processing network: Self-similar processing by unit processing cells may together solve a problem. A unit processing cell may include a processor, a memory and a plurality of Input/Output (IO) channels coupled to the processor. The memory may include a dictionary having one or more instructions that configure the processor to perform at... Agent:

20110072241 - Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded and a ticket lock per element: Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving... Agent: International Business Machines Corporation

20110072242 - Configurable processing apparatus and system thereof: A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus has a stall-output signal generating circuit to output a stall-output signal, wherein the stall-output signal indicates that an unexpected stall is occurred in the... Agent: Industrial Technology Research Institute

20110072244 - Credit-based streaming multiprocessor warp scheduling: One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that... Agent:

20110072243 - Unified collector structure for multi-bank register file: One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a... Agent:

20110072245 - Hardware for parallel command list generation: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first... Agent:

20110072246 - Node control device interposed between processor node and io node in information processing system: A node control device is interposed between processor nodes and IO nodes in an information processing system, wherein each IO node subordinates at least one IO device. The node control device includes a register storing a base address of a mapping destination of an IO space, a table describing a... Agent:

20110072247 - Fast application programmable timers: Methods, systems, and computer program products for implementing fast application programmable timers are provided. A computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a request to set a... Agent: International Business Machines Corporation

20110072248 - Unanimous branch instructions in a parallel thread processor: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take... Agent:

20110072250 - Methods and apparatus for scalable array processor interrupt detection and response: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When... Agent: Altera Corporation

20110072249 - Unanimous branch instructions in a parallel thread processor: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take... Agent:

20110072251 - Pile processing system and method for parallel processors: A system, method and computer program product are provided for processing exceptions. Initially, computational operations are processed in a loop. Moreover, exceptions are identified and stored while processing the computational operations. Such exceptions are then processed separate from the loop.... Agent: Droplet Technology, Inc.

03/17/2011 > patent applications in patent subcategories.

20110066825 - Message routing scheme: Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address... Agent: Xmos Ltd.

20110066826 - Image data processing apparatus: An image data processing apparatus includes: a plurality of operational processing circuits each of which is configured to have a variable circuit configuration and to execute operational processing on image data; and a control section that controls each of the operational processing circuits such that each of the operational processing... Agent: Fuji Xerox Co., Ltd.

20110066827 - Multiprocessor: A multiprocessor of a single processor, including a pipeline processing unit which successively fetches an instruction sequence to be independently processed on each of the multiprocessor with a shifted phase in one cycle.... Agent: Fujitsu Limited

20110066828 - Mapping of computer threads onto heterogeneous resources: Techniques are generally described for mapping a thread onto heterogeneous processor cores. Example techniques may include associating the thread with one or more predefined execution characteristic(s), assigning the thread to one or more heterogeneous processor core(s) based on the one or more predefined execution characteristic(s), and/or executing the thread by... Agent:

20110066829 - Selecting regions of hot code in a dynamic binary rewriter: An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a larger scope for transformation (e.g. optimization) than traces. Hardware samples are used to identify SRs that contain the hot code of a client... Agent:

20110066830 - Cache prefill on thread migration: Techniques for pre-filling a cache associated with a second core prior to migration of a thread from a first core to the second core are generally disclosed. The present disclosure contemplates that some computer systems may include a plurality of processor cores, and that some cores may have hardware capabilities... Agent:

20110066831 - System and method for software initiated checkpoint operations: A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code... Agent: Ibm Corporation

20110066832 - Configurable processor module accelerator using a programmable logic device: A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored... Agent: Drc Computer Corporation

20110066833 - Church-turing thesis: the turing immortality problem solved with a dynamic register machine: A new computing machine and new methods of executing and solving heretofore unknown computational problems are presented here. The computing system demonstrated here can be implemented with a program composed of instructions such that instructions may be added or removed while the instructions are being executed. The computing machine is... Agent:

20110066834 - Concurrent exception handling: Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled... Agent: Microsoft Corporation

03/10/2011 > patent applications in patent subcategories.

20110060889 - Method, system and computer-accessible medium for providing a distributed predicate prediction: Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors... Agent: Board Of Regents, University Of Texas System

20110060890 - Stream data generating method, stream data generating device and a recording medium storing stream data generating program: A stream data generating method for a computer system for generating stream data having time information applied thereto in a time series order and processing the generated stream data on the basis of a registered query. The computer system includes a storage for storing therein query information indicative of a... Agent: Hitachi, Ltd

20110060891 - Parallel pipelined vector reduction in a data processing system: A parallel processing data processing system builds at least one data structure indicating a communication schedule for a plurality of processes each having a respective one of a plurality of equal length vectors formed of multiple equal size chunks. The data processing system, based upon the at least one data... Agent: International Business Machines Corporation

20110060892 - Speculative forwarding of non-architected data format floating point results: A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands includes first and second floating-point units. The first floating-point unit is configured to speculatively forward a non-ADF result generated by the first floating-point unit to the second floating-point unit. The... Agent: Via Technologies, Inc.

20110060893 - Circuit comprising a microprogrammed machine for processing the inputs or the outputs of a processor so as to enable them to enter or leave the circuit according to any communication protocol: A circuit having at least one processor and a microprogrammed machine for processing the data which enters or leaves the processor in order to input or output the data into/from the circuit in compliance with a communication protocol.... Agent: Commissariat A L'energie Atomique Et Aux Energies Alternatives

20110060894 - Processor having reduced power consumption: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as... Agent:

03/03/2011 > patent applications in patent subcategories.

20110055516 - Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set: An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies.... Agent:

20110055517 - Method and structure of using simd vector architectures to implement matrix multiplication: A structure (and method) including a plurality of coprocessing units and a controller that selectively loads data for processing on the plurality of coprocessing units, using a compound loading instruction. The compound loading instruction includes a plurality of low-level software instructions that preliminarily processes input data in a manner predetermined... Agent:

20110055519 - Method and system for implementing a stream processing computer architecture: A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external... Agent:

20110055518 - Safe and secure multicore system: The different advantageous embodiments provide a system for partitioning a data processing system comprising a number of cores and a partitioning process. The partitioning process is configured to assign a number of partitions to the number of cores. Each partition in the number of partitions is assigned to a separate... Agent:

20110055520 - Systems, methods and apparatus for local programming of quantum processor elements: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.... Agent:

20110055521 - Microprocessor having at least one application specific functional unit and method to design same: Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techniques for automatic ISE identification have been improving; many algorithms have been proposed for choosing, given the application's source... Agent:

20110055522 - Request control device, request control method and associated processors: A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means and an identifier means. The comparing means is configured to determine if an incoming first queue unit corresponds to the same message... Agent:

20110055523 - Early branch determination: A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to... Agent:

20110055524 - Providing thread fairness in a hyper-threaded microprocessor: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements... Agent:

20110055525 - Providing thread fairness in a hyper-threaded microprocessor: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements... Agent:

20110055526 - Method and apparatus for accessing memory according to processor instruction: There is provided a method and apparatus for accessing a memory according to a processor instruction. The apparatus includes: a stack offset extractor extracting an offset value from a stack pointer offset indicating a local variable in the processor instruction; a local stack storage including a plurality of items, each... Agent:

20110055527 - Method and system for generating object code to facilitate predictive memory retrieval: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open... Agent:

20110055528 - Data processor: The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in... Agent:

20110055529 - Efficient branch target address cache entry replacement: A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch... Agent:

20110055530 - Fast rep stos using grabline operations: A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes... Agent:

20110055531 - Synchronizing commands and dependencies in an asynchronous command queue: Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and... Agent:

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