|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) February patent applications/inventions, industry category 02/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/24/2011 > patent applications in patent subcategories.
20110047348 - Processing elements, mixed mode parallel processor system, processing method by processing elements, mixed mode parallel processor method, processing program by processing elements and mixed mode parallel processing program: Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the... Agent: Scully Scott Murphy & Presser, PC
20110047349 - Processor and processor control method: A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110047350 - Partition level power management using fully asynchronous cores with software that has limited asynchronous support: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range.... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20110047351 - Routing image data across on-chip networks: A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to... Agent: Ren-sheng InternationalIPManagement Ltd. Gene I. Su
20110047352 - Memory coherence directory supporting remotely sourced requests of nodal scope: A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request... Agent: Dillon & Yudell LLP
20110047353 - Reconfigurable device: A device (1) including a reconfigurable section comprises a plurality of PEs (17) laid out having been divided into a plurality of segments and a command transmitting system (50) for transmitting commands to each PE (17). The command transmitting system (50) includes: a transmission command register (53) that is separately... Agent: Marshall, Gerstein & Borun LLP
20110047354 - Processor cluster architecture and associated parallel processing methods: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20110047355 - Offset based register address indexing: A circuit arrangement and method support offset based register address indexing, wherein register addresses to be used by an instruction are calculated using offsets to the full target register address, and the offsets are contained in the instruction and occupy less instruction space than the full address widths. An instruction... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20110047357 - Methods and apparatus to predict non-execution of conditional non-branching instructions: Efficient techniques are described for not executing an issued conditional non-branch instruction. A conditional non-branch instruction is identified as being eligible for a prediction, the prediction indicating that the eligible conditional non-branch (ECNB) instruction would not execute. The ECNB instruction executes as a no operation (NOP) instruction in response to... Agent: Qualcomm Incorporated
20110047356 - Apparatus,system,and method for managing commands of solid-state storage using bank interleave: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state... Agent: Kunzler Needham Massey & Thorpe
20110047358 - In-data path tracking of floating point exceptions and store-based exception indication: Mechanisms are provided for tracking exceptions in the execution of vectorized code. A speculative instruction is executed on a vector element of a vector. An exception condition is detected in association with the vector element based on a result of executing the speculative instruction on the vector element. A special... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20110047359 - Insertion of operation-and-indicate instructions for optimized simd code: Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20110047361 - Load/move duplicate instructions for a processor: A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.... Agent: Mission/bstz Blakely Sokoloff Taylor & Zafman LLP
20110047360 - Processor: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.... Agent: Marsh, Fischmann & Breyfogle LLP
20110047362 - Version pressure feedback mechanisms for speculative versioning caches: Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data.... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20110047363 - Microprogrammable device code tracing: A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The system comprises binary code generating means, and a tracing device. The binary code generating means form part of the device ,... Agent: Woodcock Washburn LLP
20110047364 - Recovering from an error in a fault tolerant computer system: A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.02/17/2011 > patent applications in patent subcategories.
20110040951 - Deduplicated data processing rate control: Various embodiments for deduplicated data processing rate control using at least one processor device in a computing environment are provided. A plurality of workers is configured for parallel processing of deduplicated data entities in a plurality of chunks. The deduplicated data processing rate is regulated using a rate control mechanism.... Agent: Griffiths & Seaton PLLC (ibm)
20110040952 - Simd parallel computer system, simd parallel computing method, and control program: Uniforming of the processing load is efficiently realized. Each processing element configuring an SIMD parallel computer system includes a data storage module that stores data processed or transferred, a number-of-data-sets storage device that stores number of data sets, and a front data storage device that stores the front data. Each... Agent: Mr. Jackson Chen
20110040954 - Data processing system: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a... Agent: Miles & Stockbridge PC
20110040953 - Microprocessor with microtranslator and tail microcode instruction for fast execution of complex macroinstructions having both memory and register forms: A microprocessor includes a first instruction translator that translates an instruction of an instruction set architecture of a microprocessor. The instruction may specify a first form that writes its result to a destination register or a second form that writes its result to memory. The first instruction translator generates, in... Agent: Huffman Law Group, P.C.
20110040955 - Store-to-load forwarding based on load/store address computation source information comparisons: A microprocessor includes a queue comprising a plurality of entries each configured to hold store information for a store instruction. The store information specifies sources of operands used to calculate a store address. The store instruction specifies store data to be stored to a memory location identified by the store... Agent: Huffman Law Group, P.C.
20110040956 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE),... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.02/10/2011 > patent applications in patent subcategories.
20110035567 - Actual instruction and actual-fault instructions for processing vectors: The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that optionally receives a predicate vector (which has N elements) as an input. The processor then executes the vector instruction. In the described embodiments, executing the vector instruction causes the processor... Agent: Pvf -- Apple Inc. C/o Park, Vaughan, Fleming & Dowler LLP
20110035568 - Select first and select last instructions for processing vectors: The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that uses a first input vector, a second input vector, and a control vector, and optionally a predicate vector as inputs, wherein each of the vectors includes N elements. The processor... Agent: Pvf -- Apple Inc. C/o Park, Vaughan, Fleming & Dowler LLP
20110035569 - Microprocessor with alu integrated into load unit: A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a... Agent: Huffman Law Group, P.C.
20110035570 - Microprocessor with alu integrated into store unit: A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction... Agent: Huffman Law Group, P.C.
20110035571 - On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as... Agent: Viswa Sharma Psimast, Inc
20110035572 - Computing device, information processing apparatus, and method of controlling computing device: Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit,... Agent: Staas & Halsey LLP
20110035573 - Out-of-order x86 microprocessor with fast shift-by-zero handling: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second... Agent: Huffman Law Group, P.C.02/03/2011 > patent applications in patent subcategories.
20110029756 - Method and system for decoding low density parity check codes: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes... Agent: Texas Instruments Incorporated
20110029757 - Stream processor and task management method thereof: A stream processor includes a programmable main processor MP, and a coprocessor CP that executes an extension instruction, the extension instruction being different from a basic instruction executed by the main processor MP. The main processor MP includes a coprocessor controller CPC outputting the extension instruction to the coprocessor CP,... Agent: Sughrue Mion, PLLC
20110029758 - Central processing unit measurement facility: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20110029759 - Method and apparatus for shuffling data: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20110029760 - Non-atomic scheduling of micro-operations to perform round instruction: A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction... Agent: Huffman Law Group, P.C.
20110029761 - Method and apparatus of reducing cpu chip size: A new compression method and apparatus compresses instructions embedded in a CPU chip which significantly reduces the density of storage device of storing the program. Multiple groups of instructions in the form of binary code are compressed separately by a mapping unit indicating the starting location of a group of... Agent: Chih-ta Star Sung Rm. 308. Bld. 52
20110029762 - Semiconductor device performing serial parallel conversion: A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with third... Agent: Sughrue Mion, PLLC
20110029763 - Branch predictor for setting predicate flag to skip predicated branch instruction execution in last iteration of loop processing: A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop processing is currently being executed. A unit causes the instruction... Agent: Greenblum & Bernstein, P.L.CPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
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