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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) January recently filed with US Patent Office 01/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/27/2011 > patent applications in patent subcategories. recently filed with US Patent Office

20110022820 - Systems, devices, and methods for analog processing: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits... Agent: Seed Intellectual Property Law Group PLLC

20110022821 - System and methods to improve efficiency of vliw processors: Exemplary embodiments provide microprocessors and methods to implement instruction packing techniques in a multiple-issue microprocessor. Exemplary instruction packing techniques implement instruction grouping vertically along packed groups of consecutive instructions, and horizontally along instruction slots of a multiple-issue microprocessor. In an exemplary embodiment, an instruction packing technique is implemented in a... Agent: Mccarter & English, LLP Stamford

20110022822 - Motion controller utilizing a plurality of processors: Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20110022823 - Information processing system and information processing method thereof: An information processing system includes an execution unit and a decoder. The execution unit includes a plurality of arithmetic units each having a first operation circuit that performs a first operation on a first input value and a second input value, a second operation circuit that performs a second operation... Agent: Foley And Lardner LLP Suite 500

20110022824 - Address generation unit with pseudo sum to accelerate load/store operations: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20110022825 - Creating and managing links to deduplication information: In a method of linking to information in a deduplication data sequence, a branching point is identified. The branching point is a place where a branch data sequence diverges from a parent data sequence that has been previously stored in a data deduplication process. A signature value associated with a... Agent: Kraguljac & Kalnay

  
01/20/2011 > patent applications in patent subcategories. recently filed with US Patent Office

20110016292 - Out-of-order execution in-order retire microprocessor with branch information table to enjoy reduced reorder buffer size: An out-of-order execution in-order retire microprocessor includes a branch information table comprising N entries. Each of the N entries stores information associated with a branch instruction. The microprocessor also includes a reorder buffer comprising M entries. Each of the M entries stores information associated with an unretired instruction within the... Agent: Huffman Law Group, P.C.

20110016293 - Device and method for the distributed execution of digital data processing operations: It includes means (12) for the identification, from a valued directed multi-graph made up of the union of several distinct processing graphs and divided into several valued directed sub-multi-graphs (54, 56, 58), called chunks, and whose input and output nodes are buffer memory nodes of the multi-graph, of a coordination... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20110016295 - Programmable exception processing latency: A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with said CPU, and a control register coupled with said CPU, wherein the control register is operable to set the operation mode of said CPU in at... Agent: King & Spalding LLP

20110016294 - Technique for replaying operations using replay look-ahead instructions: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20110016296 - Apparatus and method for executing fast bit scan forward/reverse (bsr/bsf) instructions: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the... Agent: Huffman Law Group, P.C.

  
01/13/2011 > patent applications in patent subcategories. recently filed with US Patent Office

20110010522 - Multiprocessor communication protocol bridge between scalar and vector compute nodes: A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor interconnect network and the indirect processor interconnect network.... Agent: Schwegman, Lundberg & Woessner, P.A.

20110010523 - Runtime configurable arithmetic and logic cell: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is... Agent: Kenyon & Kenyon LLP

20110010524 - Simd processor array system and data transfer method thereof: There is provided an SIMD processor array system in which data can be efficiently transferred between processor elements located at different distances. The SIMD processor array system includes a control processor (CP) that is capable of issuing a plurality of instructions at the same time, and a PE array that... Agent: Mr. Jackson Chen

20110010526 - Control apparatus for fast inter processing unit data exchange in an architecture with processing units of different bandwidth connection to a pipelined ring bus: Nowadays, many architectures have processing units with different bandwidth requirements which are connected over a pipelined ring bus. The proposed invention can optimize the data transfer for the case where processing units with lower bandwidth requirements can be grouped and controlled together for a data transfer, so that the available... Agent: Mr. Jackson Chen

20110010525 - On-chip and chip-to-chip routing using a processor element/router combination: A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the... Agent: Hewlett-packard Company Intellectual Property Administration

20110010527 - Processor for executing instruction stream at low cost, method for the execution, and program for the execution: A VLIW processor executes a very long instruction word containing a plurality of instructions, and executes a plurality of instruction streams at low cost. A processor executing a very long instruction word containing a plurality of instructions fetches concurrently the very long instruction words of up to M instruction streams,... Agent: Mr. Jackson Chen

20110010528 - Information processing device and vector information processing device: An information processing device implements a register renaming scheme for managing physical registers (e.g. hardware registers HR) coordinated with logical registers (e.g. software usable registers SUR) in conjunction with a renaming table. A first dedicated instruction is incorporated into an instruction set so that a free physical register is coordinated... Agent: Mr. Jackson Chen

20110010529 - Instruction execution control method, instruction format, and processor: With conventional ordered data reference instructions, an instruction which is to be the subject of an execution order guarantee cannot be separately specified, and a resource which is to be the subject of an execution order guarantee likewise cannot be specified and thus instruction movement is restricted more than necessary... Agent: Greenblum & Bernstein, P.L.C

20110010531 - Debuggable microprocessor: A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is... Agent: Huffman Law Group, P.C.

20110010530 - Microprocessor with interoperability between service processor and microcode-based debugger: A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus,... Agent: Huffman Law Group, P.C.

  
01/06/2011 > patent applications in patent subcategories. recently filed with US Patent Office

20110004740 - Data transfer apparatus, information processing apparatus and method of setting data transfer rate: A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner... Agent: Staas & Halsey LLP

20110004741 - Spilling method in register files for microprocessor: A spilling method in register files for a processor is proposed. The processor is of Parallel Architecture Core (PAC) structure, and accordingly includes a first cluster, a second cluster and a memory. Each of the first and second clusters includes a first function unit (e.g., M-Unit), a second function unit... Agent: Wpat, PC Intellectual Property Attorneys

20110004742 - Variable-cycle, event-driven multi-execution flash processor: A Multi-Execution Flash Processor core performs operations associated with accessing non-volatile semiconductor based memory units. Execution units included in the core can execute instructions requiring different numbers of clock cycles to complete by generating an event control signal in response to completing an instruction. The core can be used in... Agent: Edward J. Marshall, Attorney At Law

20110004743 - Pipe scheduling for pipelines based on destination register number: A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process instructions. At least one instruction includes a destination register specifier specifying which of said registers is... Agent: Nixon & Vanderhye P.C.

20110004744 - Data processing apparatus including reconfigurable logic circuit: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of... Agent: Marshall, Gerstein & Borun LLP

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