|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
12/2010 | Recent | 14: Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) December patent applications/inventions, industry category 12/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/30/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100332792 - Integrated vector-scalar processor: Systems and methods for improved vector data processing based on separately processing elements of a vector in multiple simultaneously executing vector element processing units are disclosed. One embodiment of the present invention is a vector processing system including a plurality of vector element processing units and a routing infrastructure. The... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100332793 - Method for scheduling start-up and shut-down of mainframe applications using topographical relationships: The illustrative embodiments provide for a computer-implemented method for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and columns. Ones of the columns represent corresponding ones of computer applications that can start or stop in parallel with each other in... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20100332794 - Unpacking packed data in multiple lanes: Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100332795 - Computer system including reconfigurable arithmetic device and reconfigurable arithmetic device: A computer system includes a central processing unit, a random-access-memory interface, a random-access memory in which addresses are allocated in an address space of the random-access-memory interface and a reconfigurable arithmetic device whose arithmetic function is capable of being dynamically changed in accordance with configuration data. The reconfigurable arithmetic device... Agent: Arent Fox LLP
20100332796 - Method and system for a cpu-local storage mechanism: Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local... Agent: Fay Kaplun & Marcin, LLP
20100332797 - Information processing apparatus, control method for information processing apparatus, and program: An information processing apparatus includes a first processing unit, a second processing unit which is different from the first processing unit, a supply unit configured to supply a clock to the first processing unit and the second processing unit, and a control unit configured to control the supply unit in... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100332798 - Digital processor and method: A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the... Agent: International Business Machines Corporation Richard Lau
20100332799 - Image processing apparatus and image processing method: According to an aspect of the present invention, there is provided an information processing apparatus including: a first processor; a second processor that has an information processing capability and a power consumption higher than those of the first processor; a temperature monitoring module configured to acquire an operating temperature of... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100332800 - Instruction control device, instruction control method, and processor: An instruction control device connects to a cache memory that stores data frequently used among data stored in a main memory. The instruction control device includes: a first free-space determining unit that determines whether there is free space in an instruction buffer; a second free-space determining unit that manages an... Agent: Staas & Halsey LLP
20100332801 - Adaptively handling remote atomic execution: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated... Agent: Trop, Pruner & Hu, P.C.
20100332802 - Priority circuit, processor, and processing method: A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit... Agent: Staas & Halsey LLP
20100332803 - Processor and control method for processor: A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first... Agent: Staas & Halsey LLP
20100332804 - Unified high-frequency out-of-order pick queue with support for speculative instructions: Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a... Agent: Mhkkg/oracle (sun)
20100332806 - Dependency matrix for the determination of load dependencies: Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick... Agent: Mhkkg/oracle (sun)
20100332805 - Remapping source registers to aid instruction scheduling within a processor: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more... Agent: Nixon & Vanderhye P.C.
20100332807 - Performing escape actions in transactions: Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations... Agent: Workman Nydegger/microsoft
20100332808 - Minimizing code duplication in an unbounded transactional memory system: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to... Agent: Workman Nydegger/microsoft
20100332809 - Methods and devices for saving and/or restoring a state of a pattern-recognition processor: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor... Agent: Fletcher Yoder (micron Technology, Inc.)
20100332810 - Reconfigurable functional unit having instruction context storage circuitry to support speculative execution of instructions: A functional unit is described. The functional unit includes a reconfigurable logic circuitry and instruction context storage circuitry to store instruction context information generated from instructions executed by the reconfigurable logic circuitry within the reconfigurable functional unit. The instructions include speculatively executed instructions.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100332811 - Speculative multi-threading for instruction prefetch and/or trace pre-build: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.... Agent: Intel Corporation C/o Cpa Global
20100332812 - Method, system and computer-accessible medium for low-power branch prediction: Examples of a method, system, and computer-accessible medium are provided which can utilize a neural branch predictor on, e.g., an analog circuit. For example, a current summation can be used instead of the digital dot-product generally used in traditional neural predictor designs. A scaling factor may also be used to... Agent: Dorsey & Whitney LLP Intellectual Property Department12/23/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100325386 - Parallel operation device allowing efficient parallel operational processing: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction... Agent: Buchanan, Ingersoll & Rooney PC
20100325387 - Arithmetic processing apparatus, processing unit, arithmetic processing system, and arithmetic processing method: An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100325388 - Multi-core parallel processing system: A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is... Agent: Lathrop & Gage LLP
20100325390 - Image processing apparatus, processing unit, and ip address managing method: An image processing apparatus includes connectors to each of which position information is allocated, processing units configured to be connected to the connectors, each of the processing units is configured to read position information, and to output an IP address of the processing unit determined based on the position information... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100325389 - Microprocessor communications system: A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to... Agent: Henneman & Associates, PLC
20100325391 - Systems and methods for initialization and link management of nics in a multi-core environment: The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core,... Agent: Choate, Hall & Stewart / Citrix Systems, Inc.
20100325392 - Hybrid multi function component system: This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of... Agent: Keohane & D'alessandro
20100325393 - Technique for performing layer 2 processing using a distributed memory architecture: A distributed memory architecture for a layer 2 processing circuit chip (50) is described. In one implementation, the layer 2 processing circuit chip (50) comprises an external memory interface configured to provide access to data packets stored in an external memory (52), a layer 2 processor (54) coupled to the... Agent: Ericsson Inc.
20100325394 - System and method for balancing instruction loads between multiple execution units using assignment history: A system and method for balancing instruction loads between multiple execution units are disclosed. One or more execution units may be represented by a slot configured to accept instructions on behalf of the execution unit(s). A decode unit may assign instructions to a particular slot for subsequent scheduling for execution.... Agent: Mhkkg/oracle (sun)
20100325395 - Dependence prediction in a memory system: Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100325396 - Multithread processor and register control method: The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to... Agent: Staas & Halsey LLP
20100325397 - Data processing apparatus and method: A data processing apparatus is described which comprises processing circuitry responsive to data processing instructions to execute integer data processing operations and floating point data processing operations, a first set of integer registers useable by the processing circuitry in executing the integer data processing operations, and a second set of... Agent: Nixon & Vanderhye P.C.
20100325398 - Running-min and running-max instructions for processing vectors: The described embodiments provide a processor for generating a result vector that contains results from a comparison operation. During operation, the processor receives a first input vector, a second input vector, and a control vector. When subsequently generating a result vector, the processor first captures a base value from a... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100325399 - Vector test instruction for processing vectors: The described embodiments provide a processor that executes a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100325400 - Microprocessor and data write-in method thereof: A microprocessor comprises a register set, a micro operations pool (Uops pool), a hazard detection unit, an execution unit, a dispatch unit, and a mask unit. The Uops pool receives a first micro operation and a second micro operation from a decoder, and reads at least one first operand of... Agent: Patterson Thuente Christensen Pedersen, P.A.
20100325401 - Method of translating n to n instructions employing an enhanced extended translation facility: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20100325402 - Data processing device and method for executing obfuscated programs: A program is obfuscated by reordering its instructions. Original instruction addresses are mapped to target addresses in an irregular way, with position dependent address steps between the addresses of logically successive instructions. Preferably pseudo-random address steps are used, for example with address steps that have mutually opposite sign with equal... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing12/16/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100318764 - System and method for managing processor-in-memory (pim) operations: A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed... Agent: Schwegman, Lundberg & Woessner, P.A.
20100318765 - Active memory command engine and method: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine,... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100318766 - Processor and information processing system: A processor includes a processing unit capable of executing single-instruction multiple-data operations; a register file configured to store data that is to be supplied to the processing unit and to be subjected to operations, and a buffer provided separately from the register file, the buffer being a buffer where an... Agent: Fujitsu Patent Center Fujitsu Management Services Of America, Inc.
20100318767 - Multiplexing auxiliary processing element and semiconductor integrated circuit: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed... Agent: Staas & Halsey LLP
20100318768 - Channel-based runtime engine for stream processing: An apparatus, including a memory device for storing a program, and a processor in communication with the memory device, the processor operative with the program to facilitate design of a stream processing flow that satisfies an objective, wherein the stream processing flow includes at least three processing groups, wherein a... Agent: F. Chau & Associates, LLC Frank Chau
20100318769 - Using vector atomic memory operation to handle data of different lengths: A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported... Agent: Schwegman, Lundberg & Woessner, P.A.
20100318770 - Electronic device, computer-implemented system, and application display control method therefor: An electronic device, a computer-implemented system, and an application display control method thereof are disclosed. The electronic device has a process unit that executes an operating system kernel, and then executes a first and a second software platform via the operating system kernel. When a first application is executed on... Agent: Wang Law Firm, Inc.
20100318771 - Combined byte-permute and bit shift unit: A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds to a shuffle instruction or a shift instruction. For a shuffle instruction, the byte permute unit uses a byte... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100318772 - Superscalar register-renaming for a stack-addressed architecture: A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP) stack specifier. The combinatorial logic for operand translation of N FP instructions per clock cycle may require N instantiated copies of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100318773 - Inclusive \"or\" bit matrix compare resolution of vector update conflict masks: A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements... Agent: Schwegman, Lundberg & Woessner, P.A.
20100318775 - Methods and apparatus for adapting pipeline stage latency based on instruction type: Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is... Agent: Peter H. Priest
20100318774 - Processor instruction graduation timeout: A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout... Agent: Schwegman, Lundberg & Woessner, P.A.12/09/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100312988 - Data processing apparatus and method for handling vector instructions: A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit... Agent: Nixon & Vanderhye P.C.
20100312989 - Register renaming of a partially updated data granule: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the... Agent: Nixon & Vanderhye P.C.
20100312990 - Communication between internal and external processors: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with... Agent: Fletcher Yoder (micron Technology, Inc.)
20100312991 - Microprocessor with compact instruction set architecture: A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100312992 - Multithread execution device and method for executing multiple threads: A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed information memory that stores target execution speed information of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100312993 - Register renaming table recovery method and system: A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID. Then, a first renamed ID corresponding to a first register is acquired from an unflushed row of the renaming-history table... Agent: Wpat, PC Intellectual Property Attorneys
20100312994 - Harq process management for carrier aggregation: A method and apparatus for use with a mobile user agent configured to be able to communicate via N carriers, the method for managing Hybrid Automatic Repeat reQuest (HARQ) processes in a communication system that uses R HARQ process indicators (HPIs) so that the system can support a maximum of... Agent: Research In Motion Corp./q&b Attn: Glenda Wolfe
20100312996 - Secure system for data transmission: The invention relates to a data transmission chain for a function of an aircraft onboard facility comprising a first computation chain and a second computation chain executing the same function as the first chain to validate the computation of the first chain, wherein the second computation chain uses the same... Agent: Baker & Hostetler LLP
20100312995 - Virtual world simulation systems and methods utilizing parallel coprocessors, and computer program products thereof: The current invention provides a virtual world simulation system capable of hosting with massive amount of concurrent players by integrating commodity parallel co-processors into servers. The current invention proposes novel parallel processing algorithms to make use of commodity parallel co-processors like a graphic processing unit (GPU) or any specialized hardware... Agent: Wpat, PC Intellectual Property Attorneys
20100313000 - Conditional operation in an internal processor of a memory device: The present techniques provide an internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be... Agent: Fletcher Yoder (micron Technology, Inc.)
20100312998 - Direct communication with a processor internal to a memory device: Devices, systems, and methods of communicating information directly to a sequencer or a buffer in a memory device are provided. In some embodiments, instructions are sent directly from an external processor to a sequencer in the memory device, and the sequencer configures the instructions for an internal processor, such as... Agent: Fletcher Yoder (micron Technology, Inc.)
20100312999 - Internal processor buffer: One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a compute engine which performs operations on operands retrieved from the buffer, and stores results of the operations... Agent: Fletcher Yoder (micron Technology, Inc.)
20100312997 - Parallel processing and internal processors: Systems, internal processors, and methods of parallel data processing in an internal processor are provided. In one embodiment, an external controller sends instructions to a memory device, and the internal processor on the memory device executes the instructions on the data. The internal processor may include one or more arithmetic... Agent: Fletcher Yoder (micron Technology, Inc.)
20100313001 - Data processing apparatus, data processing method, and computer-readable storage medium: An apparatus includes a plurality of processing modules which are connected to each other by corresponding communication unit and the modules transfer packets in a predetermined direction to execute a plurality of operations of pipeline processing. The module includes a storage unit for storing a first identification and a second... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100313002 - Preloading modules for performance improvements: Described is a technology for preloading modules, such as modules that show clinical/medical data maintained at a service, so as to reduce a user's wait time to use a module. The modules for which a user is authenticated are preloaded according to a loading order that is based upon the... Agent: Microsoft Corporation12/02/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100306502 - Digital signal processor having a plurality of independent dedicated processors: A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and... Agent: Timothy N. Trop Trop, Pruner, Hu & Miles, P.C.
20100306501 - Hybrid computer systems: A hybrid computer system is provided, including first and second computer devices. The first computer device is configured with the second computer device via a connection unit. Each of the first computer device and the second computer device is capable of operating independently when the first computer device and the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100306503 - Guaranteed prefetch instruction: A microprocessor includes a cache memory, an instruction set having first and second prefetch instructions each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory, and a memory subsystem configured to execute the first and second prefetch instructions. For... Agent: Huffman Law Group, P.C.
20100306504 - Controlling issue and execution of instructions having multiple outcomes: At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a... Agent: Nixon & Vanderhye P.C.
20100306505 - Result path sharing between a plurality of execution units within a processor: A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be... Agent: Nixon & Vanderhye P.C.
20100306506 - Microprocessor with selective out-of-order branch execution: A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and... Agent: Huffman Law Group, P.C.
20100306507 - Out-of-order execution microprocessor with reduced store collision load replay reduction: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a... Agent: Huffman Law Group, P.C.
20100306508 - Out-of-order execution microprocessor with reduced store collision load replay reduction: An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue... Agent: Huffman Law Group, P.C.
20100306509 - Out-of-order execution microprocessor with reduced store collision load replay reduction: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold an instruction pointer of a load instruction and to hold information useable to identify a store instruction that... Agent: Huffman Law Group, P.C.
20100306510 - Single cycle data movement between general purpose and floating-point registers: Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (RF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution... Agent: Marsh Fischmann & Breyfogle LLP (oracle Formerly D/b/a Sun Microsystems)
20100306511 - Communication data processor and communication data processing method: There is a need for providing a communication data processor easily adaptable to network configurations required for industrial Ethernet. The apparatus successively analyzes received packets. The apparatus uses a register to determine whether or not to transmit the received packet as transmission data to another port. Rewritable memory saves a... Agent: Mattingly & Malur, P.C.
20100306512 - Compiler technique for efficient register checkpointing to support transaction roll-back: A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point... Agent: Barnes & Thornburg, LLP
20100306513 - Processor core and method for managing program counter redirection in an out-of-order processor pipeline: A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100306514 - Correlating instruction sequences with cpu performance events to improve software performance: A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the... Agent: Hamilton & Terrile, LLP - Amd
20100306516 - Information processing apparatus and branch prediction method: An information processor includes a first recording unit which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent branch instruction, a computation of the most recent branch instruction having been completed and a branch for the most recent branch prediction having... Agent: Staas & Halsey LLP
20100306515 - Predictors with adaptive prediction threshold: An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine... Agent: Duke W. Yee Yee & Associates, P.C.Previous industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20140306:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.57362 seconds