|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) November recently filed with US Patent Office 11/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/25/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100299496 - Thread partitioning in a multi-core environment: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries... Agent: Dillon & Yudell LLP
20100299497 - Apparatus for efficiently determining instruction length within a stream of x86 instruction bytes: An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture. The apparatus includes combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the... Agent: Huffman Law Group, P.C.
20100299498 - Information processing apparatus and information processing method: An information processing apparatus includes: a first pipeline having first nodes, and moving data held in each first node to a first node located in a first direction; a second pipeline having second nodes corresponding to the first nodes, and moving data held in each second node to a second... Agent: Fitzpatrick Cella Harper & Scinto
20100299499 - Dynamic allocation of resources in a threaded, heterogeneous processor: Systems and methods for efficient dynamic utilization of shared resources in a processor. A processor comprises a front end pipeline, an execution pipeline, and a commit pipeline, wherein each pipeline comprises a shared resource with entries configured to be allocated for use in each clock cycle by each of a... Agent: Mhkkg/oracle (sun)
20100299502 - Bad branch prediction detection, marking, and accumulation for faster instruction stream processing: An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decode logic decodes the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator and... Agent: Huffman Law Group, P.C.
20100299501 - Instruction extraction through prefix accumulation: An apparatus has a queue, each entry stores a different line of a stream of instruction bytes and accumulated prefix information associated with each instruction byte. Control logic: (a) detects a condition where an initial portion of an instruction partially within a first line stored in the bottom entry (BE)... Agent: Huffman Law Group, P.C.
20100299500 - Prefix accumulation for efficient processing of instructions with multiple prefix bytes: In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of... Agent: Huffman Law Group, P.C.
20100299503 - Apparatus and method for marking start and end bytes of instructions in a stream of instruction bytes in a microprocessor having an instruction set architecture in which instructions may include a length-modifying prefix: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction... Agent: Huffman Law Group, P.C.
20100299504 - Microprocessor with microinstruction-specifiable non-architectural condition code flag register: A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first... Agent: Huffman Law Group, P.C.
20100299505 - Instruction fusion calculation device and method for instruction fusion calculation: An instruction fusion calculation device of the present invention includes an instruction fusion detection circuit, an instruction fusion circuit, and a calculator. The instruction fusion detection circuit determines whether or not a fusion of a preceding instruction and a subsequent instruction that have a flow dependence relationship between them can... Agent: Mr. Jackson Chen
20100299506 - Rotate then operate on selected bits facility and instructions therefore: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register.... Agent: International Business Machines Corporation Richard Lau
20100299507 - On-line testing for decode logic: Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100299508 - Dynamically allocated store queue for a multithreaded processor: Systems and methods for storage of writes to memory corresponding to multiple threads. A processor comprises a store queue, wherein the queue dynamically allocates a current entry for a committed store instruction in which entries of the array may be allocated out of program order. For a given thread, the... Agent: Mhkkg/oracle (sun)
20100299509 - Simulation system, method and program: A computer-implemented pipeline execution system, method, and program product for executing loop processing in a multi-core or a multiprocessor computing environment, where the loop processing includes multiple function blocks in a multiple-stage pipeline manner. The system includes: a pipelining unit for pipelining the loop processing and assigning the loop processing... Agent: Ibm Corporation, T.j. Watson Research Center11/18/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100293356 - Method and system for managing hardware resources to implement system functions using an adaptive computing architecture: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures,... Agent: Nixon Peabody, LLP
20100293357 - Method and apparatus for providing platform independent secure domain: A platform independent secure domain providing apparatus, which determines whether an execution environment is to be in a secure domain and a non-secure domain by a secure bit. The apparatus includes a secure monitor that is adapted to generate a branch instruction when a call to a secure code is... Agent: Lee & Morse, P.C.
20100293358 - Dynamic processor-set management: A dynamic processor-set management method provides for transferring a process from a shared processor set to a dedicated processor set when that process meets a first utilization-related criterion. The method also provides for transferring a process between from a dedicated processor set to a shared processor set when that process... Agent: Hewlett-packard Company Intellectual Property Administration
20100293359 - General purpose register cloning: A clone set of General Purpose Registers (GPRs) is created to be used by a set of helper thread binaries, which is created from a set of main thread binaries. When the set of main thread binaries enters a wait state, the set of helper thread binaries uses the clone... Agent: Dillon & Yudell LLP11/11/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100287357 - Computer memory architecture for hybrid serial and parallel computing systems: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions... Agent: Gamburd Law Group LLC
20100287358 - Branch prediction path instruction: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess... Agent: Cantor Colburn LLP-ibm Yorktown
20100287359 - Variable register and immediate field encoding in an instruction set architecture: A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code... Agent: Townsend And Townsend And Crew LLP/mips
20100287360 - Task processing device: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and... Agent: Carr & Ferrell LLP
20100287361 - Root cause analysis for complex event processing: Root cause analysis for complex event processing is described. In embodiments, root cause analysis at a complex event processor is automatically performed by selecting an output event from an operator and correlating the output event to an input event using event type and lifetime data for the input event and... Agent: Lee & Hayes, PLLC11/04/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100281234 - Interleaved multi-threaded vector processor: A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data... Agent: Stevens Law Group
20100281235 - Reconfigurable floating-point and bit-level data processing unit: Blocks of fixed-point units in a reconfigurable data processing unit assist the efficient calculation of floating decimal point numbers by virtue of joint hardware functions permanently implemented within the block.... Agent: Kenyon & Kenyon LLP
20100281236 - Apparatus and method for transferring data within a vector processor: An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly... Agent: Stevens Law Group
20100281237 - Information processing apparatus, information processing method, and computer-readable storage medium: In an information processing apparatus in which data processing is performed in a predetermined sequence by processing modules connected to a ring bus, if an amount of data generated by input data in the ring bus is not considered, the data amount exceeds an amount of data that can be... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100281238 - Execution of instructions directly from input source: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC
20100281239 - Reliable execution using compare and transfer instruction on an smt machine: A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a mission critical software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100281241 - Method and system for synchronizing inclusive decision branches: A method and system for reconstructing an original process model that includes an inclusive decision into a reconstructed process model that includes synchronized branches. The inclusive decision is replaced with a fork. Each original path of the inclusive decision is reconstructed into a corresponding reconstructed path. Each reconstructed path includes... Agent: Schmeiser, Olsen & Watts
20100281240 - Program code simulator: A system and method for facilitating simulation of a computer program. A program representation is generated from a computer program. A simulation of the program is performed. Simulation may include applying heuristics to determine program flow for selected instructions, such as a branch instruction or a loop instruction. Simulation may... Agent: Microsoft CorporationPrevious industry: Electrical computers and digital processing systems: memory
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