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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) October categorized by USPTO classification 10/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
10/28/2010 > patent applications in patent subcategories.

20100274988 - Flexible vector modes of operation for simd processor: In addition to the usual modes of SIMD processor operation, where corresponding elements of two source vector registers are used as input pairs to be operated upon by the execution unit, or where one element of a source vector register is broadcast for use across the elements of another source... Agent: Sawyer Law Group, P.C.

20100274989 - Accelerating traceback on a signal processor: A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2b bits, using selected b bits of the... Agent: Barnes & Thornburg LLP

20100274990 - Apparatus and method for performing simd multiply-accumulate operations: An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required... Agent: Nixon & Vanderhye P.C.

20100274991 - Risc processor device and method of simulating floating-point stack operation thereof: An RISC processor device and a method of emulating a floating-point stack operation thereof The processor device comprises: a floating-point register file containing a plurality of floating-point registers; a decoding section for decoding operation instructions of the RISC processor; a floating-point operation section connected to the decoding section; a control... Agent: Occhiuti Rohlicek & Tsao, LLP

20100274992 - Apparatus and method for handling dependency conditions: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these... Agent: Mhkkg/oracle (sun)

20100274993 - Logical map table for detecting dependency conditions: Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical... Agent: Mhkkg/oracle (sun)

20100274995 - Processor and method of controlling instruction issue in processor: One exemplary embodiment includes a processor including a plurality of execution units and an instruction unit. The instruction unit discriminates whether an instruction is a target instruction for which determination about availability of parallel issue based on dependency among instructions is to be made with respect to each instruction contained... Agent: Sughrue Mion, PLLC

20100274994 - Processor operating mode for mitigating dependency conditions: Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction... Agent: Mhkkg/oracle (sun)

20100274996 - Micro-processor: A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program... Agent: Ampacc Law Group

20100274997 - Executing a gather operation on a parallel computer: Methods, apparatus, and computer program products are disclosed for executing a gather operation on a parallel computer according to embodiments of the present invention. Embodiments include configuring, by the logical root, a result buffer or the logical root, the result buffer having positions, each position corresponding to a ranked node... Agent: Ibm (roc-blf)

10/21/2010 > patent applications in patent subcategories.

20100268911 - Method and apparatus for dynamic partial reconfiguration on an array of processors: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing... Agent: Henneman & Associates, PLC

20100268912 - Thread mapping in multi-core processors: Techniques for thread mapping in multi-core processors are disclosed. An example computing system is disclosed having a multi-core processor with a plurality of processor cores. A performance counter may be configured to collect data relating to the performance of the multi-core processor. A core controller may be configured to map... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100268913 - Lithographic apparatus, control system, multi-core processor, and a method to start tasks on a multi-core processor: A multi-core processor includes two or more cores; an external communication facility that is shared by the cores and is capable of communicating with one of the cores at a time; and an internal communication facility capable of communicating simultaneously with each one of the cores; wherein the multi-core processor... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20100268914 - Processing system with interspersed processors and dynamic pathway creation: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100268915 - Remote update programming idiom accelerator with allocated processor resources: A data processing system comprises at least one processing unit, a virtualization layer, and a remote update programming idiom accelerator. The remote update programming idiom accelerator is configured to receive a complex remote update programming idiom from a remote node. Responsive to a determination that the sequence of instructions in... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100268916 - Risc processor and its register flag bit processing method: The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack... Agent: Occhiuti Rohlicek & Tsao, LLP

20100268918 - Asip architecture for executing at least two decoding methods: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system... Agent: Knobbe Martens Olson & Bear LLP

20100268917 - Systems and methods for ramped power state control in a semiconductor device: Various embodiments of the present invention provide systems and methods for ramping current usage in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include at least a first function circuit and a second function circuit, and a power state change control circuit. The... Agent: Hamilton,desanctis & Cha (lsi)

20100268919 - Method and structure for solving the evil-twin problem: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different... Agent: Gunnison, Mckay & Hodgson, L.L.P.

20100268920 - Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor: A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation... Agent: Mhkkg/oracle (sun)

20100268921 - Data collection prefetch device and methods thereof: A method of retrieving information from a memory includes receiving an instruction associated with a data collection. In response to determining the instruction is a request to retrieve a first element of the data collection, an application program interface (API) generates an instruction to prefetch a second element of the... Agent: Larson Newman & Abel, LLP

20100268922 - Processor that utilizes re-configurable logic to construct persistent finite state machines from machine instruction sequences: A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC... Agent: Christopher Joseph Daffron

20100268923 - Method and device for controlling a computer system having at least two groups of internal states: A method and device for controlling a computer system having at least two execution units and having at least two groups of internal states, in particular processor states, in at least one of the execution units, and having a switchover device, through which it is possible to switch between at... Agent: Kenyon & Kenyon LLP

- None available for 10/01/2010

- None available for 10/7/2010

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