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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) September class, title,number 09/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
09/30/2010 > patent applications in patent subcategories.

20100250897 - Addressing device for parallel processor: The invention relates to a parallel processor which comprises elementary processors (3) disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result. The... Agent: Lariviere, Grubman & Payne, LLP

20100250899 - Distributed processing system: A distributed processing system includes a plurality of processing elements each having one or more inputs and one or more outputs, and a control unit to which the plurality of processing elements are connected, wherein based on a service execution request from a client, the control unit creates execution transition... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100250898 - Processing element and distributed processing unit: A general-purpose processing element has a program holding portion that can hold a program by which a specific function is implemented in the general-purpose processing element. A distributed processing system according to the invention includes a control unit, a plurality of processing elements connected to the control unit, and a... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100250900 - Dependency tracking for enabling successive processor instructions to issue: An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100250901 - Selecting fixed-point instructions to issue on load-store unit: Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20100250902 - Tracking deallocated load instructions using a dependence matrix: A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100250903 - Apparatuses and systems including a software application adaptation layer and methods of operating a data processing apparatus with a software adaptation layer: A software application adaptation layer is comprised of a program file comprising a plurality of adaptation filters and a configuration file. The configuration file may designate one or more adaptation filters of the plurality of adaptation filters to be applied by the program file for modifying one or more behaviors... Agent: Madson Ip

20100250904 - Methods and processor-related media to perform rapid returns from subroutines in microprocessors and microcontrollers: Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single... Agent: Schwegman, Lundberg & Woessner / Atmel

20100250905 - System and method of routing instructions: Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more embodiments, an instruction steering unit of the superscalar processor receives ordered instructions. The steering unit determines that a first instruction... Agent: Dillon & Yudell LLP

20100250906 - Obfuscation: In an embodiment of a method of making a conditional jump in a computer running a program, an input is provided, conditional on which a substantive conditional branch is to be made. An obfuscatory unpredictable datum is provided. Code is executed that causes an obfuscatory branch conditional on the unpredictable... Agent: Drinker Biddle & Reath Attn: Intellectual Property Group

09/23/2010 > patent applications in patent subcategories.

20100241823 - Data processing device and method: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher... Agent: Kenyon & Kenyon LLP

20100241824 - Processing array data on simd multi-core processor architectures: Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20100241825 - Opportunistic transmission of software state information within a link based computing system: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100241826 - Data processing apparatus, data processing method and program: A data processing apparatus can reduce an occupancy rate of a ring bus by suppressing occurrence of a stall packet, and can change a processing sequence. In the data processing apparatus, a buffer is provided in each communication unit connecting the ring bus and the associated processing unit. Transfer of... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100241828 - General distributed reduction for data parallel computing: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are automatically translated into a distributed execution plan. Map and reduction computations are automatically added to the plan. Patterns in the sequential program can be automatically identified to... Agent: Vierra Magen/microsoft Corporation

20100241829 - Hardware switch and distributed processing system: A hardware switch to which a plurality of processing elements are connected, wherein for sending side processing elements and receiving side processing elements different from the sending side processing elements selected from among the plurality of processing elements, the hardware switch interconnects one output selected from outputs that the sending... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100241827 - High level programming extensions for distributed data parallel processing: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. A set of extensions to a sequential high-level computing language are provided to support distributed... Agent: Vierra Magen/microsoft Corporation

20100241831 - Data packet processing method for a multi core processor: A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection to a network between the network and a designated CPU core, such that for all data packets... Agent: Hewlett-packard Company Intellectual Property Administration

20100241830 - Transfer triggered microcontroller with orthogonal instruction set: A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and... Agent: North Weber & Baugh LLP

20100241832 - Instruction fetching following changes in program flow: This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to... Agent: Nixon & Vanderhye P.C.

20100241833 - Information processing apparatus: Disclosed is an information processing apparatus in which various kinds of information are processed in either the real time processing mode or the non-real time processing mode. The apparatus includes an operation display section to accept an inputted instruction, an image processing section to apply a processing to image information... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100241834 - Method of encoding using instruction field overloading: The method selects registers by a register instruction field having x bits. A first group of registers has up to 2y registers and a second group of registers has up to 2z registers where y and z are at least one and not great than x. The method includes encoding... Agent: Barnes & Thornburg LLP

20100241835 - Processor with automatic scheduling of operations: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand... Agent: Stmicroelectronics, Inc.

09/16/2010 > patent applications in patent subcategories.

20100235607 - Processor: A processor includes a setting register in which a mode is set, a general-purpose register including a preferred slot used during scalar computing and a slot not used during the scalar computing, a selector configured to select and output data of a register designated by a mode set in the... Agent: SprinkleIPLaw Group

20100235608 - Method and apparatus for game physics concurrent computations: An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is coupled to the PU. The PU broadcasts data to... Agent: Sughrue Mion, PLLC

20100235609 - Ring-pattern bus connected information processing apparatus, information processing method, and storage medium: In an information apparatus including a plurality of processing circuits connected to a ring bus, when processing speeds (throughput) of processing circuits are different or an amount of data in the processing circuit is increased or decreased, deadlock can occur or the throughput can be decreased in the ring bus.... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100235610 - Processing system, processing apparatus and computer readable medium: A processing apparatus includes: an operation detection unit that detects an operation; a request unit that requests other processing apparatuses to transmit functions when the operation is detected by the operation detection unit; a receiving unit that receives replies in response to the requests of the request unit from the... Agent: Sughrue-265550

20100235611 - Compiler, compile method, and processor core control method and processor: A compiler compiling a source code and is implemented in a plurality of processor cores includes a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent... Agent: Arent Fox LLP

20100235612 - Macroscalar processor architecture: A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that... Agent: Apple Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20100235613 - Method, apparatus or software for processing exceptions produced by an application program: A method, apparatus and software is disclosed in which original exceptions issued by an application program are encoded as substitute exceptions with associated metadata identifying the original exception so as to enable to enable a first application program receiving the exception but not arranged to process the original exception to... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

09/09/2010 > patent applications in patent subcategories.

20100228949 - Processors: A processing apparatus comprises a plurality of processors (12), each arranged to perform an instruction, and a bus (20) arranged to carry data and control tokens between the processors. Each processor (12) is arranged, if it receives a control token via the bus, to carry out the instruction, and on... Agent: Fraser Clemens Martin & Miller LLC

20100228950 - Microprocessor with fast execution of call and return instructions: A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state... Agent: Huffman Law Group, P.C.

20100228951 - Parallel processing management framework: The present disclosure includes a management framework system for processing a parallel task. The framework includes a job package, a job submitter, task trackers, communicators, a plurality of processors, and a node service. The job package has a bundle of implementations defined by a user and an input data domain.... Agent: Xerox Corporation (cdfs)

20100228952 - Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction... Agent: Huffman Law Group, P.C.

20100228953 - Reducing data hazards in pipelined processors to provide high processor utilization: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100228954 - General purpose embedded processor: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting... Agent: Nutter Mcclennen & Fish LLP

20100228955 - Method and apparatus for improved power management of microprocessors by instruction grouping: A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining... Agent: Scully, Scott, Murphy & Presser, P.C.

20100228956 - Control circuit, information processing device, and method of controlling information processing device: A control circuit for receiving data transmitted by a data transmitting circuit and transmitting the received data to a data receiving circuit includes: a data receiving unit for receiving the data transmitted by the data transmitting circuit; a packet analyzing unit for judging whether the data received from the data... Agent: Fujitsu Patent Center Fujitsu Management Services Of America, Inc.

20100228957 - Systems and methods for branch prediction override during process execution: Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction replacement circuit, and an execution pipeline. The branch target buffer includes a... Agent: Hamilton,desanctis & Cha (lsi)

09/02/2010 > patent applications in patent subcategories.

20100223444 - Method for performing plurality of bit operations and a device having plurality of bit operations capabilities: A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information... Agent: Reches Patents

20100223445 - Method and apparatus for matrix decompositions in programmable logic devices: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks... Agent: Townsend And Townsend And Crew LLP/ 015114

20100223446 - Contextual tracing: A method of tracking execution of activities in a computing environment in which events in an activity are recorded along with an activity identifier uniquely identifying the activity and tying the events to the activity. To track interactions between activities, a correlation identifier may be generated and transferred between the... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.

20100223448 - Computer configuration virtual topology discovery and instruction therefore: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology... Agent: International Business Machines Corporation Richard Lau

20100223447 - Translate and verify instruction for a processor: In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that specifies one or more translation attributes that exist in a page table entry that defines a translation for... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20100223449 - Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus: An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a... Agent: North Star Intellectual Property Law, PC

20100223450 - Information processing device, information processing method and computer readable medium: A storage part stores correspondence information on incorporation or change in processing sequence of processing elements. An acquiring part acquires a target processing element group. An extracting part extracts the correspondence information on the processing elements included in the target processing element group. An incorporation determining part determines a set... Agent: Sughrue-265550

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