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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) August inventions list 08/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
08/26/2010 > patent applications in patent subcategories. inventions list

20100217954 - Method and apparatus for obtaining a scalar value directly from a vector register: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector... Agent: Nixon & Vanderhye, P.C.

20100217955 - Routing across multicore networks using real world or modeled data: The present disclosure relates to a system for routing data across a multicore processing network. The system includes a multicore processing array having a plurality of processing cores, a memory for storing data relating to an object being modeled, the data being associated with coordinate information relating to the object... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100217956 - Companion chip for a microcontroller: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module... Agent: Kenyon & Kenyon LLP

20100217957 - Structured virtual registers for embedded controller devices: Techniques for using structured virtual registers in embedded systems are described. A virtual register structure definition provides a map of virtual registers within an embedded controller. The virtual registers are externally accessible and correspond to memory locations within the embedded controller. In various embodiments, an embedded controller and/or an external... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100217958 - Address calculation and select-and-insert instructions within data processing systems: A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon... Agent: Nixon & Vanderhye P.C.

20100217959 - Information processing apparatus, virtual storage management method, and storage medium: A virtual storage management method that can increase the overall processing speed while preventing a processor from being overloaded. A request for acquisition of a memory area in a primary storage device is received from a process executed by a processor. It is determined whether or not the process that... Agent: Rossi, Kimms & Mcdowell LLP.

20100217960 - Method of performing serial functions in parallel: A method for performing serial functions in parallel, where a datapath is divided into several independent stages, or pipeline stages, so that logical functions can be implemented in each pipeline stage concurrently. In an illustrative embodiment of the invention, a pipelined logic tree is described. This method allows for n-bits... Agent: Avalon Microelectronics, Inc. Attn: Intellectual Property

20100217961 - Processor system executing pipeline processing and pipeline processing method: A processor system includes a plurality of pipeline stages, a controller, and a transfer path. The plurality of pipeline stages is subjected to processing. The controller determines whether or not each of the executable instructions to be processed in the pipeline stages requires processing in a succeeding pipeline stage. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100217962 - Predicting a conditional bit value for continuing execution of an instruction: Methods and microprocessors are provided for continuing execution of an instruction, even though execution of the instruction depends on a value of a conditional bit (e.g., a flag bit or a predicated bit) that has not been determined. Rather than stalling execution of the instruction, a predicted value of the... Agent: Duft Bornsen & Fishman LLP

  
08/19/2010 > patent applications in patent subcategories. inventions list

20100211757 - Systolic data processing apparatus and method: A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control... Agent: F. Chau & Associates, LLC

20100211758 - Microprocessor and memory-access control method: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of... Agent: Turocy & Watson, LLP

20100211759 - Apparatus and method for generating vliw, and processor and method for processing vliw: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a... Agent: North Star Intellectual Property Law, PC

20100211760 - Apparatus and method for providing instruction for heterogeneous processor: Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided... Agent: North Star Intellectual Property Law, PC

20100211761 - Digital signal processor (dsp) with vector math instruction: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A... Agent: Texas Instruments Incorporated

20100211762 - Mechanism for efficient implementation of software pipelined loops in vliw processors: A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program... Agent: Rahman LLC

20100211763 - Data broadcast processing device, method and program: The present invention relates to a data broadcast processing device, method, and program which enable secure control of an operation of a data broadcast processing device. Since a flag standalone is not set in a script NCL Script 133, the script NCL Script 133 is executed from time t13 till... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

  
08/12/2010 > patent applications in patent subcategories. inventions list

20100205398 - Transmission device and swichover processing method: In an optical transmission device, firmware that operates within a CPU of a first LIU and firmware that operates within a CPU of a second LIU periodically measure a load status of a CPU via an OS, respectively. Switchover control of a master CPU is performed according to a load... Agent: Staas & Halsey LLP

20100205399 - Performance counter for microcode instruction execution: An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address... Agent: Huffman Law Group, P.C.

20100205400 - Executing routines between an emulated operating system and a host operating system: Approaches for emulating an operating system. A method includes executing a first operating system (OS) on an instruction processor. The first OS includes instructions of a first instruction set that are native to the instruction processor. A second OS is emulated on the first OS and includes instructions of a... Agent: Unisys Corporation

20100205403 - Pipelined microprocessor with fast conditional branch instructions based on static exception state: A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes... Agent: Huffman Law Group, P.C.

20100205404 - Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state: A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is... Agent: Huffman Law Group, P.C.

20100205401 - Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution: A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional... Agent: Huffman Law Group, P.C.

20100205402 - Pipelined microprocessor with normal and fast conditional branch instructions: A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state... Agent: Huffman Law Group, P.C.

20100205405 - Static branch prediction method and code execution method for pipeline processor, and code compiling method for static branch prediction: A static branch prediction method and code execution method for a pipeline processor, and a code compiling method for static branch prediction, are provided herein. The static branch prediction method includes predicting a conditional branch code as taken or not-taken, adding the prediction information, converting the conditional branch code into... Agent: North Star Intellectual Property Law, PC

20100205406 - Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register: An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register of the microprocessor. A comparator compares the new value specified by the architectural segment register-loading instruction with a current contents of the architectural segment register. A... Agent: Huffman Law Group, P.C.

20100205407 - Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution: A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a prediction of conditional branch instructions of the first type and flushes the pipeline of instructions if the prediction is subsequently determined to be... Agent: Huffman Law Group, P.C.

20100205408 - Speculative region: hardware support for selective transactional memory access annotation using instruction prefix: A computer system and method is disclosed for executing selectively annotated transactional regions. The system is configured to determine whether an instruction within a plurality of instructions in a transactional region includes a given prefix. The prefix indicates that one or more memory operations performed by the processor to complete... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20100205409 - Novel register renaming system using multi-bank physical register mapping table and method thereof: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a... Agent: Stmicroelectronics, Inc.

20100205410 - Data processing: Apparatus for data processing includes a processor, memory and storage. A plurality of sets of instructions, each corresponding to one of a plurality of programs, is stored in the storage. The processor is configured to load the sets of instructions from the storage into the memory, identify a first program... Agent: Richard M. Goldberg

20100205411 - Handling complex regex patterns storage-efficiently using the local result processor: A result processor access a result table for an entry associated with a predetermined sub-expression of a regular expression in response to a finite state machine finding the predetermined sub-expression in the input stream. The result processor executes an instruction associated with the entry, the instruction including one or more... Agent: Scully, Scott, Murphy & Presser, P.C.

20100205412 - Control sequencer: An audio codec (100) is provided with a control sequencer (110) interposed between control interface logic (120) and control registers (130) of the codec. A memory (114, 116) associated with the control sequencer (110) enables a burst of operations to be preloaded into the audio codec. In response to a... Agent: Dickstein Shapiro LLP

20100205413 - Translated memory protection: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction,... Agent: Iv (transmeta) C/o Murabito, Hao & Barnes LLP

20100205414 - High integrity processor monitor: A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring... Agent: Honeywell/fogg Patent Services

20100205415 - Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state: A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value... Agent: Huffman Law Group, P.C.

  
08/05/2010 > patent applications in patent subcategories. inventions list

20100199067 - Split vector loads and stores with stride separated words: A method, system and computer program product are presented for causing a parallel load/store of stride-separated words from a data vector using different memory chips in a computer.... Agent: Ibm Corporation

20100199068 - Reconfigurable processor for reduced power consumption and method thereof: Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register... Agent: North Star Intellectual Property Law, PC

20100199069 - Scheduler of reconfigurable array, method of scheduling commands, and computing apparatus: A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources... Agent: North Star Intellectual Property Law, PC

20100199071 - Data processing apparatus and image processing apparatus: A data processing apparatus in which pipeline processing is performed comprises a control unit that controls a data processing sequence, a first processing unit that begins first data processing by inputting data on the basis of a start signal, outputs data subjected to the first data processing, and outputs a... Agent: Straub & Pokotylo

20100199070 - Programmable filter processor: A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw... Agent: Kenyon & Kenyon LLP

20100199072 - Register file: A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request received at said at least one... Agent: Nixon & Vanderhye P.C.

20100199073 - Multithreaded processor with multiple concurrent pipelines per thread: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20100199074 - Instruction set architecture with decomposing operands: Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new... Agent: Cantor Colburn LLP - IBM Tuscon Division

20100199075 - Multithreaded processor with multiple concurrent pipelines per thread: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20100199076 - Computing apparatus and method of handling interrupt: A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform... Agent: North Star Intellectual Property Law, PC

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