|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) July category listing 07/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/29/2010 > patent applications in patent subcategories. category listing
20100191933 - Apparatus for processing data and method for generating manipulated and re-manipulated configuration data for processor: Some embodiments comprise an apparatus for processing data, the apparatus having a second configurable processor configured to process data using second configuration data, and a configuration data re-manipulator configured to retrieve manipulated second configuration data and first data of a first processor, to re-manipulate the manipulated second configuration data depending... Agent: Dickstein Shapiro LLP
20100191934 - Microcomputer and dividing circuit: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having... Agent: Mattingly & Malur, P.C.
20100191935 - Architecture and implementation method of programmable arithmetic controller for cryptographic applications: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the... Agent: Lsi Corporation C/o Suiter Swantz PC Llo
20100191936 - Method and system for operating-system-independent power management using performance verifications: Systems and methods are disclosed for power management in information handling systems using processor performance data to validate changes to processor performance states. Processor utilization data and processor performance data is obtained during system operation. The processor utilization data is analyzed to determine a desired performance state for the processor.... Agent: O'keefe, Egan, Peterman & Enders LLP
20100191937 - Implied storage operation decode using redundant target address detection: A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100191938 - Information processing device, arithmetic processing method, electronic apparatus and projector: An information processing device including: a first arithmetic processing unit performing first arithmetic processing; a second arithmetic processing unit performing second arithmetic processing; input registers adapted to include a first input register allocated to the first arithmetic processing unit, and a second input register allocated to the second arithmetic processing... Agent: Oliff & Berridge, PLC
20100191939 - Trigonometric summation vector execution unit: A unique instruction and exponent adjustment adder selectively shift outputs from multiple execution units, including a plurality of multipliers, in a processor core in order to scale mantissas for related trigonometric functions used in a vector dot product.... Agent: Ibm Corporation
20100191940 - Single step mode in a software pipeline within a highly threaded network on a chip microprocessor: A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is dispatched as an appended work packet granule to a... Agent: Ibm Corporation
20100191941 - Failure analysis apparatus, method: A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the... Agent: Sughrue Mion, PLLC
20100191942 - Information processor and control method: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU... Agent: Staas & Halsey LLP
20100191943 - Coordination between a branch-target-buffer circuit and an instruction cache: A digital signal processor (DSP) having (i) a processing pipeline for processing instructions received from an instruction cache (I-cache) and (ii) a branch-target-buffer (BTB) circuit for predicting branch-target instructions corresponding to received branch instructions. The DSP reduces the number of I-cache misses by coordinating its BTB and instruction pre-fetch functionalities.... Agent: Mendelsohn, Drucker, & Associates, P.C.07/22/2010 > patent applications in patent subcategories. category listing
20100185832 - Data moving processor: A system and method for processing data is disclosed. In one embodiment, a data moving processor comprises a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address... Agent: Slater & Matsil LLP
20100185833 - Multiprocessor control apparatus, multiprocessor control method, and multiprocessor control circuit: An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which... Agent: Wenderoth, Lind & Ponack L.L.P.
20100185834 - Data storing method and processor using the same: A data storing method applied to a processor having a pipelined processing unit is provided. The pipelined processing unit includes stages. The stages include a source operand fetch stage and a write-back stage. The method includes the following steps. Firstly, a storing instruction is fetched and decoded. Next, the storing... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100185835 - Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the... Agent: Leydig Voit & Mayer, Ltd
20100185836 - Arithmetic program conversion apparatus, arithmetic program conversion method, and program: An arithmetic-program conversion apparatus includes: a program storage section storing an arithmetic program describing a circuit by a logical expression including a plurality of input and output variables, and operators; if the expression has three input variables or more, an intermediate-variable generation section generating an intermediate variable for converting the... Agent: Wolf Greenfield & Sacks, P.C.
20100185837 - Reconfigurable logic automata: A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured... Agent: Norma E Henderson Henderson Patent Law
20100185838 - Processor assigning control system and method: A processor assigning control system includes a first memory to store a plurality of control instructions and loading schedules, a second memory to temporarily store the plurality of control instructions and loading schedules, a real-time clock (RTC), and a main controller. The main controller includes a hardware detecting unit, a... Agent: PCe Industry, Inc. Att. Steven Reiss
20100185839 - Apparatus and method for scheduling instruction: An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When scheduling a plurality of recurrence loops, the apparatus first schedules a... Agent: North Star Intellectual Property Law, PC
20100185840 - Propagating unobserved exceptions in a parallel system: A method of handling an exception in a parallel system includes constructing a task object, executing a method with the task object, and catching an exception with the task object during execution of the method. The exception is propagated in response to the task object becoming inaccessible without the exception... Agent: Microsoft Corporation07/15/2010 > patent applications in patent subcategories. category listing
20100180100 - Matrix microprocessor and method of operation: A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according... Agent: Law Offices Of Michael M. Ahmadshahi
20100180101 - Method for executing one or more programs on a multi-core processor and many-core processor: The invention relates to a method for executing computer usable program code or a program made up of program parts on a multi-core processor (1) with a multiplicity of execution units (21, 22, 23, 24), each of which comprises a local memory (201) and at least one processing unit (202)... Agent: Jansson Shupe & Munger Ltd.
20100180102 - Enhancing processing efficiency in large instruction width processors: The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one... Agent: D. Kligler I.p. Services Ltd
20100180103 - Mechanism for increasing the effective capacity of the working register file: A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is... Agent: Gunnison, Mckay & Hodgson, L.L.P.
20100180104 - Apparatus and method for patching microcode in a microprocessor using private ram of the microprocessor: A microprocessor has a microcode memory for storing original microcode instructions to implement user program instructions, and an interface to an external memory for storing a microcode patch. The microcode patch includes substitute microcode instructions and validation information. The microprocessor includes a private random access memory (PRAM), addressable by the... Agent: Huffman Law Group, P.C.
20100180105 - Modifying commands: The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the... Agent: Brooks, Cameron & Huebsch , PLLC
20100180106 - Asynchronous checkpointing with audits in high availability networks: Example embodiments are directed to methods of ensuring high availability of a network using asynchronous checkpointing of application state data related to an object. Example embodiments include a method of asynchronous checkpointing application state data related to at least one object, including receiving application events and processing the application events... Agent: Harness, Dickey & Pierce, P.L.C07/08/2010 > patent applications in patent subcategories. category listing
20100174883 - Processor architectures for enhanced computational capability and low latency: A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow... Agent: Goodwin Procter LLP Patent Administrator
20100174884 - Processor having reconfigurable arithmetic element: A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable arithmetic element (125) having a circuit configuration that is dynamically reconfigurable; and an arithmetic operation control... Agent: Greenblum & Bernstein, P.L.C
20100174885 - Reconfigurable processor and operating method of the same: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration... Agent: North Star Intellectual Property Law, PC
20100174886 - Multi-core processing utilizing prioritized interrupts for optimization: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized... Agent: Texas Instruments Incorporated
20100174887 - Buses for pattern-recognition processors: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form... Agent: Fletcher Yoder (micron Technology, Inc.)
20100174888 - Memory system: A memory system includes a storage device storing a plurality of instructions and a central processing unit processing an instruction fetched from the storage device, wherein the central processing unit detects a change in the instruction fetched from the storage device while processing the instruction.... Agent: F. Chau & Associates, LLC
20100174889 - Guest-specific microcode: Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate... Agent: Intel Corporation C/o Cpa Global
20100174890 - Known good code for on-chip device management: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100174891 - Reconfigurable simd processor and method for controlling its instruction execution: In a reconfigurable SIMD processor, a unit of operation for executing an instruction corresponds to one group, and the one group that includes a plurality of PEs implements at least a part of an operation unit that executes at least one of an integer divide instruction: a floating decimal point... Agent: Mr. Jackson Chen
20100174892 - Multiprocessor system and method for synchronizing a debugging process of a multiprocessor system: The invention relates to a method and a system for synchronizing a debugging process of a multiprocessor system (1) with a number of processors (2.1 to 2.3), comprising the following steps: —if for one of the processors (2.1 to 2.3) a debugging process is requested by a STOP-signal (STOP#2.1 to... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100174893 - Runtime checking of dynamic subranges: Software defects (e.g., array access out of bounds, stack overflow, infinite loops, and data corruption) occur due to integer values falling outside their expected range. Because programming languages do not include range-checking instructions as part of their language, to detect software defects and ensure that the code runs smoothly, programmers... Agent: Ibm Austin Iplaw (dg)07/01/2010 > patent applications in patent subcategories. category listing
20100169607 - Reconfigurable circuit, its design method, and design apparatus: A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in... Agent: Arent Fox LLP
20100169608 - Flexible counter update and retrieval: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units... Agent: Harrity & Harrity, LLP
20100169609 - Method for optimizing voltage-frequency setup in multi-core processor systems: A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a... Agent: Intel Corporation C/o Cpa Global
20100169610 - Processor: The processor according to the present invention is a processor having a forwarding function and includes an attribute information holding unit that holds attribute information regarding inhibition of writing to a register and a register write inhibition circuit that holds, when forwarding is performed, the writing of the data forwarded... Agent: Greenblum & Bernstein, P.L.C
20100169611 - Branch misprediction recovery mechanism for microprocessors: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and... Agent: Mhkkg/oracle (sun)
20100169612 - Data-processing unit for nested-loop instructions: A data-processing unit has a fetching circuitry (20) and execution circuitry (30a, 30b). The data-processing unit has an instruction set comprising a nested-loop instruction. The fetching circuitry is arranged to fetch the nested-loop instruction, and the execution circuitry is arranged to execute the nested-loop instruction. The nested-loop instruction comprises at... Agent: Potomac Patent Group PLLC
20100169613 - Translating instructions in a speculative processor: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor... Agent: Iv (transmeta) C/o Murabito, Hao & Barnes LLP
20100169614 - Processor for executing highly efficient vliw: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the... Agent: Mcdermott Will & Emery LLP
20100169615 - Preloading instructions from an instruction set other than a currently executing instruction set: A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded... Agent: Qualcomm Incorporated
20100169617 - Power efficient system for recovering an architecture register mapping table: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a... Agent: Stmicroelectronics, Inc.
20100169616 - Reducing instruction collisions in a processor: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order... Agent: Stmicroelectronics, Inc.
20100169618 - Identifying concurrency control from a sequential proof: The claimed subject matter provides a system and/or a method that facilitates ensuring non-interference between multiple threads that access a shared resource. An interface can receive a portion of sequential code, wherein the portion of sequential code includes a property that is maintained and relied upon when invoked and executed... Agent: Microsoft Corporation
20100169619 - Efficient encoding for detecting load dependency on store with misalignment: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask,... Agent: Mhkkg, PC/apple, Inc.
20100169620 - Signal processing device, signal processing method, and program: There is provided a signal processing device which is capable of suppressing the influence of a digital data process on an analog signal process without completely stopping a digital data processing circuit. A signal processing device includes an analog signal processing circuit, a digital data processing circuit, a determination section... Agent: Wolf Greenfield & Sacks, P.C.
20100169621 - Processor test apparatus, processor test method, and processor test program: A processor test method of testing a processor includes executing each test instruction of a test instruction sequence to obtain a condition code set by a condition code setting instruction of the test instruction sequence for testing the processor; producing a condition branching instruction to add the produced condition branching... Agent: Fujitsu Management Services Of America, Inc.
20100169622 - Processor register recovery after flush operation: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction... Agent: Mark P. Kahler
20100169623 - Method and system for reducing abort rates in speculative lock elision using contention management mechanisms: Hardware-based transactional memory mechanisms, such as Speculative Lock Elision (SLE), may allow multiple threads to concurrently execute critical sections protected by the same lock as speculative transactions. Such transactions may abort due to contention or due to misidentification of code as a critical section. In various embodiments, speculative execution mechanisms... Agent: Mhkkg/oracle (sun)
20100169624 - Adaptive fetch advance control for a low power processor: A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a program in the DSP, the... Agent: Texas Instruments Incorporated
20100169625 - Reducing branch checking for non control flow instructions: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or... Agent: Stmicroelectronics, Inc.
20100169626 - System and method for a multi-schema branch predictor: A system and method for predicting the execution of a branch of computer-executable instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash... Agent: Stmicroelectronics, Inc.
20100169627 - System and method for repairing a speculative global history record: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch... Agent: Gerald W. Maliszewski
20100169628 - Controlling non-redundant execution in a redundant multithreading (rmt) processor: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and... Agent: Trop, Pruner & Hu, P.C.Previous industry: Electrical computers and digital processing systems: memory
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