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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) June invention type 06/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
06/24/2010 > patent applications in patent subcategories. invention type

20100161938 - System-on-a-chip supporting a networked array of configurable symmetric multiprocessing nodes: An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means... Agent: Gordon & Jacobson, P.C.

20100161940 - Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures,... Agent: Nixon Peabody, LLP

20100161939 - Parallel processing method and system, for instance for supporting embedded cluster platforms, computer program product therefor: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the... Agent: Seed Intellectual Property Law Group PLLC

20100161942 - Information handling system including a processor with a bifurcated issue queue: An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQ 0... Agent: Mark P. Kahler

20100161941 - Method and system for improved flash controller commands selection: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among... Agent: Nvidia C/o Murabito, Hao & Barnes LLP

20100161943 - Processor capable of power consumption scaling: The present invention relates to a processor capable of power consumption scaling, and more particularly, to a technique that variably controls the energy consumption of a processor according to the energy capacity being supplied by providing a pipeline register with a bypass function so as to control the operating frequency... Agent: Ampacc Law Group

20100161944 - Processor and instruction control method: An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some of bit fields belonging to a plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC

20100161945 - Information handling system with real and virtual load/store instruction issue queue: An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100161946 - Controlling jittering effects: Methods and related systems for controlling jitter effects are disclosed.... Agent: Fish & Richardson PC

20100161947 - Pack unicode zseries instructions: Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20100161948 - Apparatus and method for processing complex instruction formats in a multi-threaded architecture supporting various context switch modes and virtualization schemes: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20100161950 - Semi-absolute branch instructions for efficient computers: Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20100161949 - System and method for fast branching using a programmable branch table: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table... Agent: Akin Gump Strauss Hauer & Feld, LLP

20100161951 - Processor and method for recovering global history shift register and return address stack thereof: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage... Agent: J C Patents

  
06/17/2010 > patent applications in patent subcategories. invention type

20100153684 - Modular avionics system of an aircraft: A modular avionics system includes several cabinets arranged at various locations in an aircraft and interconnected in a network. The cabinets are used for controlling or processing signals from and to sensors, actuators and other systems of the aircraft. The system includes parallel processors, for example transputers. The cabinets comprise... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20100153685 - Multiprocessor system: m

20100153686 - Coprocessor unit with shared instruction stream: A processor unit and a coprocessor unit are disclosed. In one embodiment, the processor unit includes a functional unit that receives a set of instructions in an instruction stream and provides the set of instructions to the coprocessor unit. The coprocessor executes the instructions and initiates transmission of a set... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20100153687 - Streaming processor, operation method of streaming processor and processor system: There is provided a streaming processor which includes one general-purpose processor core and multiple operation processor cores and which performs parallel processing by assigning multiple processes of decoding processing of an encoded stream to the operation processor cores. The streaming processor performs stream analysis processing for estimating a processing load... Agent: SprinkleIPLaw Group

20100153688 - Apparatus and method for data process: An exemplary aspect of the present invention is a data processing apparatus for processing a loop in a pipeline that includes an instruction memory and a fetch circuit that fetches an instruction stored in the instruction memory. The fetch circuit includes an instruction queue that stores an instruction to be... Agent: Young & Thompson

20100153689 - Processor instruction used to determine whether to perform a memory-related trap: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the... Agent: Van Pelt, Yi & James LLP

20100153690 - Using register rename maps to facilitate precise exception semantics: One embodiment of the present invention provides a system that facilitates precise exception semantics. The system includes a processor that uses register rename maps to support out-of-order execution, where the register rename maps track mappings between native architectural registers and physical registers for a program executing on the processor. These... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20100153691 - Lower power assembler: A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps: generating a set of multiple-instruction words (INS(i), INS(i+1), INS(i+2)), wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field... Agent: Leydig Voit & Mayer, Ltd

20100153692 - Media action script acceleration apparatus: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of... Agent: Gamburd Law Group LLC

20100153693 - Code execution with automated domain switching: Within the field of computing, many scenarios involve the execution of an instruction set within a domain that is configured to support an execution context. However, various portions of the instruction set may be preferably executed in different domains, such as for promoting performance and for providing debugging features like... Agent: Microsoft Corporation

20100153694 - Program and information processing apparatus: A computer readable medium includes: storing an evaluation value and relating, to a plurality of evaluating target information, the evaluation value indicative of a possibility that a second processing for sequentially executing a first processing that is predetermined for each of the evaluating target information is successful; updating the evaluation... Agent: Sughrue-265550

  
06/10/2010 > patent applications in patent subcategories. invention type

20100146241 - Modified-simd data processing architecture: An apparatus and method for processing data includes an array of processing elements to simultaneously perform operations on multiple data elements using a single instruction. A grouping module assigns each processing element within the array to one of several groups. A modification module designates how each group of processing elements... Agent: Stevens Law Group

20100146242 - Data processing apparatus and method of controlling the data processing apparatus: Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data into the selected stream processor. The stream processor status information... Agent: Staas & Halsey LLP

20100146243 - Transaction aware, flexible interface for a state correlation and transition execution engine: The subject matter disclosed herein provides methods and apparatus, including computer program products, for state alignment and transaction coupling to enable reliable communication between an application, such as a backend system, and a correlation engine (or rules engine). In one aspect there is provided a method. The method may provide... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.

20100146244 - Method for instructing a data processor to process data: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format.... Agent: Mcdermott Will & Emery LLP

20100146246 - Method and apparatus for decompression of block compressed data: System and method for decompressing data. A compressed data stream including contiguous variable length blocks is received, each block including multiple contiguous variable length data fields and a tag portion that includes multiple contiguous tag fields corresponding respectively to the data fields. Each tag field stores a tag value specifying... Agent: Mhkkg / Globalfoundries

20100146245 - Parallel execution of a loop: A method of executing a loop over an integer index range of indices in a parallel manner includes assigning a plurality of index subsets of the integer index range to a corresponding plurality of threads, and defining for each index subset a start point of the index subset, an end... Agent: Microsoft Corporation

20100146247 - Method and system for managing out of order dispatched instruction queue with partially de-coded instruction stream: A computer-implemented method and apparatus for managing an out of order dispatched instruction queue in a microprocessor. In one embodiment, the method and apparatus include assigning a group identification number and a target identification number to an instruction in an instruction stream. The group identification number and the target identification... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20100146248 - Methods and apparatus for performing jump operations in a digital processor: Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a... Agent: Goodwin Procter LLP Patent Administrator

20100146249 - Control-flow prediction using multiple independent predictors: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall... Agent: Dorsey & Whitney LLP Intellectual Property Department

  
06/03/2010 > patent applications in patent subcategories. invention type

20100138631 - Process for qr transformation using a cordic processor: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having... Agent: Jay Chesavage

20100138632 - Programmable cordic processor with stage re-use: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having... Agent: Jay Chesavage

20100138633 - Variable clocked heterogeneous serial array processor: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an... Agent: Connolly Bove Lodge & Hutz LLP

20100138634 - Devices, systems, and methods to synchronize parallel processing of a single data stream: Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal.... Agent: Fletcher Yoder (micron Technology, Inc.)

20100138635 - Systems and methods for managing endian mode of a device: Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian operating mode or a little-endian operating mode. The device may include a register in which the current endian mode of the device is indicated in at... Agent: Fletcher Yoder (micron Technology, Inc.)

20100138637 - Data processing method: A data processing method for sampling data from data each varying over time, each of the data being associated with each of grid points arranged in an area, the method includes: dividing the area into blocks; calculating a variation rate of each of the data associated with each of the... Agent: Staas & Halsey LLP

20100138636 - Method of sending an executable code to a reception device and method of executing this code: One embodiment of the present invention discloses a process for sending an executable code to a security module locally connected to a receiving device. This security module comprises a microcontroller and a memory, the memory including at least one executable area provided to contain instructions suitable to be executed by... Agent: Harness, Dickey & Pierce, P.L.C

20100138638 - System and method of instruction modification: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment... Agent: Iv (transmeta) C/o Murabito, Hao & Barnes LLP

20100138639 - Sandboxed execution of plug-ins: A sandbox architecture that isolates and identifies misbehaving plug-ins (intentional or unintentional) to prevent system interruptions and failure. Based on plug-in errors, the architecture automatically disables and blocks registration of the bad plug-in via a penalty point system. Publishers of bad plug-ins are controlled by disabling the bad plug-ins and... Agent: Microsoft Corporation

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