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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) May archived by USPTO category 05/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/27/2010 > patent applications in patent subcategories. archived by USPTO category
20100131737 - Method for manipulating data in a group of processing elements to perform a reflection of the data: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element... Agent: Jones Day
20100131738 - Array processor type data processing apparatus: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings... Agent: Mr. Jackson Chen
20100131739 - Integrated circuit having data processing stages and electronic device including the integrated circuit: An integrated circuit (100) is disclosed that comprises a plurality of data processing stages (110) and a data communication network comprising a plurality of data communication paths between the data processing stages (110). Each data processing stage (110) comprises a hardware layer (160) for processing data received through a data... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100131740 - Data processing system and data processing method: The workload is heavy in the development of an application program that controls the task distribution in consideration of the variety of the execution environment. In a system where the processing is distributed to SPUs serving as plural processing entities so as to execute the computer program, the data processing... Agent: Katten Muchin Rosenman LLP
20100131741 - Multi-core microcontroller having comparator for checking processing result: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are... Agent: Brundidge & Stanger, P.C.
20100131743 - Lazy and stateless events: Event-based processing is employed in conjunction with lazy and stateless events. Addition of any handlers is deferred until a user-specified handler is identified. Furthermore, event handlers can be composed at this time including the same properties as underlying events. More specifically, handlers specified on composite events can be composed and... Agent: Turocy & Watson, LLP
20100131742 - Out-of-order execution microprocessor that selectively initiates instruction retirement early: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor... Agent: Huffman Law Group, P.C.
20100131744 - Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment: A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having... Agent: Texas Instruments Incorporated
20100131745 - Exceptional events: An event-driven system enables handlers to be specified for success and failure, among other things. In other words, events can be explicitly encoded with an option of returning either a success or a failure result. In this manner, asynchronous programming and events can be unified. Multiple event streams can be... Agent: Microsoft Corporation05/20/2010 > patent applications in patent subcategories. archived by USPTO category
20100125718 - Parallel analysis of time series data: In one aspect, a method of processing time-ordered multi-element data uses a set of computational nodes. In some examples, hundreds or thousands of nodes are used. A set of portions of the data are accepted, for example, from a MD simulation system. Each portion of the data is associated with... Agent: Occhiuti Rohlicek & Tsao, LLP
20100125717 - Synchronization controller for multiple multi-threaded processors: A gated-storage system including multiple control interfaces, each control interface operatively connected externally to respective multithreaded processors. The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit... Agent: The Law Office Of Michael E. Kondoudis
20100125720 - Instruction mode identification apparatus and method: An instruction mode identification apparatus includes a program counter and a processor. The program counter stores an instruction address, which comprises a plurality of bits for indicating an address of an instruction currently executed or to be executed. At least one of the plurality of bits is a redundant bit.... Agent: Vedder Price P.C.
20100125719 - Instruction target history based register address indexing: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction.... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100125721 - System and method for determining and/or reducing costs associated with utilizing objects: According to one embodiment of the present invention, a method includes receiving, in near real time, data associated with a utilization of one or more objects. The method further includes comparing the data associated with the utilization of the one or more objects with one or more rules associated with... Agent: Baker Botts L.L.P.
20100125722 - Multithreaded processing unit with thread pair context caching: A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of... Agent: Wood, Herron & Evans, L.L.P. (ibm)05/13/2010 > patent applications in patent subcategories. archived by USPTO category
20100122063 - Information processing apparatus and method: A read-only memory (ROM) includes storage areas used as a processing setting data storage unit, a successful detection rate storage unit, and a processing time storage unit. A central processing unit (CPU) can function as a calculation unit by executing a calculation program stored on the ROM. The successful detection... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100122064 - Method for increasing configuration runtime of time-sliced configurations: A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory.... Agent: Kenyon & Kenyon LLP
20100122065 - System and method for large-scale data processing using an application-independent framework: A large-scale data processing system and method for processing data in a distributed and parallel processing environment. The system includes an application-independent framework for processing data having a plurality of application-independent map modules and reduce modules. These application-independent modules use application-independent operators to automatically handle parallelization of computations across the... Agent: Morgan, Lewis & Bockius LLP/google
20100122067 - Across-thread out-of-order instruction dispatch in a multithreaded microprocessor: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution,... Agent: Townsend And Townsend And Crew LLP
20100122066 - Instruction method for facilitating efficient coding and instruction fetch of loop construct: Instruction set techniques have been developed to identify explicitly the beginning of a loop body and to code a conditional loop-end in ways that allow a processor implementation to efficiently manage an instruction fetch buffer and/or entries in an instruction cache. In particular, for some computations and processor implementations, a... Agent: Zagorin O'brien Graham LLP (115)
20100122068 - Multithreaded processor with multiple concurrent pipelines per thread: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective... Agent: Patent Docket Administrator Lowenstein Sandler P.C.
20100122069 - Macroscalar processor architecture: A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an... Agent: Apple Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20100122070 - Combined associative and distributed arithmetics for multiple inner products: Subvector slices x(i,r,s) of a first vector x(i) are stored (e.g., in a CAM array) in a bit-parallel word-serial manner. For each of the stored subvector slices and in parallel on bits of said each subvector slice, an operation is executed that outputs a pre-calculated inner product result of the... Agent: Harrington & Smith
20100122071 - Semiconductor device and data processing method: A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100122072 - Debugging system, debugging method, debugging control method, and debugging control program: A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units (51, 52) that perform arithmetic processing; a comparison unit (53) that compares outputs from the plurality of arithmetic processing units (51, 52); and a debug processing unit (54) that outputs a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100122073 - Handling exceptions in software transactional memory systems: A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such... Agent: Intel Corporation C/o Cpa Global05/06/2010 > patent applications in patent subcategories. archived by USPTO category
20100115232 - Large integer support in vector operations: A vector processor or vector processing computer has a first vector register operable to store two or more vector elements that together comprise a single first large integer and a second vector register operable to store two or more vector elements that together comprise a single second large integer. An... Agent: Schwegman, Lundberg & Woessner, P.A.
20100115234 - Configurable vector length computer processor: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more... Agent: Schwegman, Lundberg & Woessner, P.A.
20100115233 - Dynamically-selectable vector register partitioning: The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a... Agent: Fulbright & Jaworski L.l.p
20100115235 - Eliminating synchronous grace period detection for non-preemptible read-copy update on uniprocessor systems: A technique for optimizing grace period detection in a uniprocessor environment. An update operation is performed on a data element that is shared with non-preemptible readers of the data element. A call is issued to a synchronous grace period detection method. The synchronous grace period detection method performs synchronous grace... Agent: Walter W. Duft
20100115236 - Hierarchical shared semaphore registers: A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the... Agent: Schwegman, Lundberg & Woessner, P.A.
20100115237 - Co-processor infrastructure supporting dynamically-modifiable personalities: A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a... Agent: Fulbright & Jaworski L.l.p
20100115238 - Stream processing system having a reconfigurable memory module: A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number... Agent: Occhiuti Rohlicek & Tsao, LLP
20100115239 - Variable instruction width digital signal processor: A DSP architecture achieves high code density and performance by using 16 bit encoding/decoding of three-register instructions and including orthogonal 64 register selection fields within a 32-bit instruction. A 64 entry register file allows high performance, while the 16-bit instruction size provides excellent code density in control type applications.... Agent: Wilmerhale/boston
20100115240 - Optimizing performance of instructions based on sequence detection or information associated with the instructions: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the... Agent: Trop, Pruner & Hu, P.C.
20100115243 - Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor: A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100115242 - Engine/processor cooperation system and cooperation method: To provide an engine software cooperation mechanism which avoids stopping the operation of a high-speed engine during timer monitoring processing. This system checks occurrence of a timeout event by directly accessing the content of a session data memory without regard to the locking state of a session. If detecting the... Agent: Mr. Jackson Chen
20100115244 - Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency: A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100115245 - Detecting and recovering from timing violations of a processor: A system for detecting and correcting invalid calculation results due to a timing violation. A processor compares results of an instruction simultaneously executed by a first arithmetic pipeline and a second arithmetic pipeline of the processor. In the second arithmetic pipeline, the critical stage of the first arithmetic pipeline is... Agent: Dillon & Yudell LLP
20100115246 - System and method of data partitioning for parallel processing of dynamically generated application data: An improved system and method of data partitioning for parallel processing of dynamically generated application data is provided. An application may send a request to partition the application data specified by a data partitioning policy and to process each of the data partitions according to processing instructions. The data partitioning... Agent: Law Office Of Robert Bolan
20100115247 - Replacement policy for hot code detection: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution... Agent: Caven & Aghevli LLC C/o Cpa Global
20100115248 - Technique for promoting efficient instruction fusion: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.... Agent: Intel Corporation C/o Cpa Global
20100115250 - Context switching and synchronization: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20100115249 - Support of a plurality of graphic processing units: Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configuration register configured to send instructions related... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100115251 - Method, system, and computer program product for optimizing runtime branch selection in a flow process: A method, system, and computer program product for optimizing runtime branch selection in a flow process are provided. The method includes gathering performance metrics of flow branch behavior for executed flows in a runtime system over time and using aggregated performance metrics for the behavior to determine an optimal ordering... Agent: Cantor Colburn LLP - IBM FishkillPrevious industry: Electrical computers and digital processing systems: memory
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