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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) April category listing, related patent applications 04/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
04/29/2010 > patent applications in patent subcategories.

20100106939 - Transferring data from integer to vector registers: A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to... Agent: Stephen C. Kaufman IBM Corporation, Intellectual Property Law Dept.

20100106940 - Processing unit with operand vector multiplexer sequence control: Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed by the vector-based execution unit. A swizzle sequence instruction is defined in an instruction set for the vector-based execution unit... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20100106941 - Multi-core stream processing system, and scheduling method for the same: In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N≧2. When the scheduler receives a stream element from a Pth stream fetching unit, the scheduler assigns... Agent: Occhiuti Rohlicek & Tsao, LLP

20100106942 - Risc microprocessor architecture implementing multiple typed register sets: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100106943 - Processing device: It is possible to realize fetch of instructs constituting a loop by using a simple configuration without fixing a loop start point. Provided is a processing method performed by a processing device including: a instruction buffer; a instruction decoder; a pointer arranged to correspond to the instruction buffer and indicating... Agent: Staas & Halsey LLP

20100106944 - Data processing apparatus and method for performing rearrangement operations: A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An... Agent: Nixon & Vanderhye P.C.

20100106945 - Instruction processing apparatus: The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective instructions belonging to different threads and decoded by the decode section;... Agent: Staas & Halsey LLP

20100106946 - Method for processing stream data and system thereof: The present invention provides a method for processing stream data and a system thereof capable of implementing general data processing including recursive processing with low latency. In the system for processing stream data, a single operator graph is prepared from operator trees of a plurality of queries, an execution order... Agent: Mattingly & Malur, P.C.

20100106947 - Processor exploiting trivial arithmetic operations: The present application relates to the field of processors and in particular to the carrying out of arithmetic operations. Many of the computations performed by processors consist of a large number of simple operations. As a result, a multiplication operation may take a significant number of clock cycles to complete.... Agent: Marsh, Fischmann & Breyfogle LLP

20100106948 - Managing an out-of-order asynchronous heterogeneous remote direct memory access (rdma) message queue: A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location... Agent: Ibm Austin Iplaw (c/o)

20100106949 - Source code processing method, system and program: A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an original source code by an input device into the computing apparatus; finding a critical path in the original source code... Agent: Ibm Corporation, T.j. Watson Research Center

20100106950 - Method and system for loading status control of dll: Apparatus and methods are provided for controlling the loading status of DLLs. Specifically, a streaming program compiler is provided. The compiler includes operation modules for calling DLLs during streaming program execution; association table generating units for generating association tables according to user-defined rules, where the association table includes entries indicating... Agent: Ibm Corporation, T.j. Watson Research Center

04/22/2010 > patent applications in patent subcategories.

20100100703 - System for parallel computing: A system and a method for parallel computing for solving complex problems is envisaged. Particularly, hierarchical parallel computing system is envisaged by this invention, which is formed by multiple levels of groups, where each group consists of multiple processing elements. Each group of the parallel computing system models as processing... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100100704 - Integrated circuit incorporating an array of interconnected processors executing a cycle-based program: An integrated circuit 4 is provided including an array 10 of processors 26 with interface circuitry 12 providing communication with further processing circuitry 14. The processors 26 within the array 10 execute individual programs which together provide the functionality of a cycle-based program. During each program-cycle of the cycle based... Agent: Nixon & Vanderhye P.C.

20100100705 - Distributed processing system, distributed processing method and computer program: A distributed processing system includes at least two processing elements (100 and 200) which are mutually connected, and each processing element having at least a processing section, a memory section, and a communication section. A first processing section (102) stores data in a predetermined area of a first memory section... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100100706 - Multiple processor system, system structuring method in multiple processor system and program thereof: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment... Agent: Mr. Jackson Chen

20100100707 - Data structure for controlling an algorithm performed on a unit of work in a highly threaded network on a chip: A computer-implemented method, system and computer program product for controlling an algorithm that is performed on a unit of work in a subsequent software pipeline stage in a Network On a Chip (NOC) is presented. In one embodiment, the method executes a first operation in a first node of the... Agent: Ibm Corporation

20100100710 - Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method: According to an aspect of the embodiment, when data on a cache RAM is rewritten in a storage processing of one thread, an determination unit searches a fetch port which holds a request of another thread, checks whether a request exists whose processing is completed, whose instruction is a load... Agent: Staas & Halsey LLP

20100100709 - Instruction control apparatus and instruction control method: In a CPU having a SMT function of executing plural threads composed of a series of instructions representing processing, there are provided a decode section for decoding processing represented by instructions of plural threads, an instruction buffer for obtaining instructions from a thread and holding the instructions, and inputting the... Agent: Staas & Halsey LLP

20100100708 - Processing device: A processing device which can execute a plurality of threads includes: an execution unit which executes a command; a supply unit which supplies a command to the execution unit; a buffer unit which holds the command supplied from the supply unit; and a control unit which manages the buffer unit.... Agent: Staas & Halsey LLP

20100100711 - Data processor device and methods thereof: A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at... Agent: Larson Newman & Abel, LLP

20100100712 - Multi-execution unit processing unit with instruction blocking sequencer logic: A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20100100713 - Fast floating point compare with slower backup for corner cases: A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare... Agent: Cantor Colburn LLP - IBM Tuscon Division

20100100714 - System and method of indirect register access: Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect... Agent: Fletcher Yoder (micron Technology, Inc.)

20100100715 - Handling debugger breakpoints in a shared instruction system: A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that... Agent: Martin & Associates, LLC

04/15/2010 > patent applications in patent subcategories.

20100095086 - Dynamically aligning enhanced precision vectors based on addresses corresponding to reduced precision vectors: Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100095087 - Dynamic data driven alignment and data formatting in a floating-point simd architecture: Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100095088 - Reconfigurable elements: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.... Agent: Kenyon & Kenyon LLP

20100095090 - Barrier synchronization method, device, and multi-core processor: A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong... Agent: Staas & Halsey LLP

20100095089 - Multiprocessor system with multiport memory: A multiprocessor system includes first and second processors independently executing application functions associated with one or more applications using an open operating system (OS), a multiport memory, a first nonvolatile memory coupled to the first processor via a first bus, and a second nonvolatile memory coupled to the second processor... Agent: Volentine & Whitt PLLC

20100095093 - Information processing apparatus and method of controlling register: An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register and a work register provided for each thread and for... Agent: Staas & Halsey LLP

20100095092 - Instruction execution control device and instruction execution control method: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed for a predetermined period during simultaneous multi-thread operation, and controls such that... Agent: Staas & Halsey LLP

20100095095 - Instruction processing apparatus: An instruction processing apparatus includes a thread execution processing section executing threads each including plural instructions, a register file including a register window having plural registers, a current window pointer indicating a position of the register where the register window is possible to be inputted and outputted, a current register... Agent: Staas & Halsey LLP

20100095094 - Method for processing data: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first... Agent: Kenyon & Kenyon LLP

20100095091 - Processor, method and computer program: To accelerate processing speed of a processor while keeping increased complexity in the processor's circuitry to a minimum. A processor is offered, comprising a decoder which sequentially acquires and decodes an instruction from a program, including an instruction of a first type and a second type, which are classified according... Agent: Potomac Patent Group PLLC

20100095096 - Av device and its control method: In an AV device control, from unit instructions (210, 220, 230) for executing a series of operations, input parts (211, 221, 231) for allowing user inputs to be inputted are respectively extracted and the extracted input parts (211, 221, 231) are concatenated as a first process, and execution parts (212,... Agent: Mcdermott Will & Emery LLP

20100095097 - Floating point only single instruction multiple data instruction set architecture: Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100095098 - Generating and executing programs for a floating point single instruction multiple data instruction set architecture: Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20100095099 - System and method for storing numbers in first and second formats in a register file: A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.... Agent: Cantor Colburn LLP-ibm Europe

20100095101 - Capturing context information in a currently occurring event: According to a sample embodiment, a method is provided for capturing context information about an event. A data collector is created comprising instructions to collect specific context data in response to specific conditions in a call stack, and the data collector is registered with a first failure data capture application.... Agent: Steven E. Bach Attorney At Law

20100095100 - Checkpointing a hybrid architecture computing system: A method, apparatus, and program product checkpoint an application in a parallel computing system of the type that includes a plurality of hybrid nodes. Each hybrid node includes a host element and a plurality of accelerator elements. Each host element may include at least one multithreaded processor, and each accelerator... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20100095102 - Indirect branch processing program and indirect branch processing method: A processor reads an interpreter program to start an interpreter. The interpreter makes branch prediction by executing, in place of an indirect branch instruction that is necessary for execution of a source program, storing branch destination addresses in the indirect branch instruction in a link register (the processor internally stacks... Agent: Greer, Burns & Crain

20100095103 - Instruction execution control device and instruction execution control method: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in... Agent: Staas & Halsey LLP

04/08/2010 > patent applications in patent subcategories.

20100088488 - Quantum gate method and apparatus: A method includes causing a common-resonator mode resonating with a transition between |2>i and |3>i that are coupled to each other by a transition having a homogenous broadening ΔEhomo greater than an energy difference between |0>i and |1>i, an energy difference between |2>i and |3>i being greater than ΔEhomo, transferring... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100088489 - data transfer network and control apparatus for a system with an array of processing elements each either self-or common controlled: A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20100088490 - Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator: In accordance with exemplary implementations, application computation operations and communications between operations on a host processing platform may be adapted to conform to the memory capacity of a parallel accelerator. Computation operations may be split and scheduled such that the computation operations fit within the memory capacity of the accelerator.... Agent: Nec Laboratories America, Inc.

20100088491 - Processing unit: A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of... Agent: Staas & Halsey LLP

20100088492 - Systems and methods for implementing best-effort parallel computing frameworks: Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing... Agent: Nec Laboratories America, Inc.

20100088493 - Image processing device and data processor: A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside... Agent: Brundidge & Stanger, P.C.

20100088494 - Total cost based checkpoint selection: A method, system, and computer usable program product for total cost based checkpoint selection are provided in the illustrative embodiments. A cost associated with taking a checkpoint is determined. The cost includes an energy cost. An interval between checkpoints is computed so as to minimize the cost. An instruction is... Agent: Ibm Corp. (gig)

20100088495 - Mode-specific container runtime attachment: The operation of a multi-mode application. The multi-mode application has a number of mode-specific logical containers of components. Each mode-specific container contains components that assist the multi-mode application in operating in a corresponding mode. If the application transitions to another mode, the component(s) of the other corresponding mode-specific logical container... Agent: Workman Nydegger/microsoft

20100088496 - Method and system for executing an executable file: A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the... Agent: Osha Liang L.L.P./sun

04/01/2010 > patent applications in patent subcategories.

20100082938 - Delegated virtualization across physical partitions of a multi-core processor (mcp): This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or... Agent: Keohane & D'alessandro

20100082939 - Techniques for efficient implementation of brownian bridge algorithm on simd platforms: Methods and apparatus for implementing Brownian Bridge algorithm on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, a memory stores a plurality of data corresponding to an SIMD (Single Instruction, Multiple Data) instruction. A processor may include a plurality of SIMD lanes. Each of the plurality... Agent: Caven & Aghevli LLC C/o Cpa Global

20100082940 - Information processor: An information processor controls accesses to a cache memory from application software programs differing in range of addresses, accesses to which are authorized. The cache memory blocks an access to an unauthorized address. In the information processor, an ID is assigned to each application software program, and the tag field... Agent: Miles & Stockbridge PC

20100082941 - Delegated virtualization in a multi-core processor (mcp): The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior... Agent: Keohane & D'alessandro

20100082942 - Virtualization across physical partitions of a multi-core processor (mcp): Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number... Agent: Keohane & D'alessandro

20100082943 - Dynamic reconfiguration support apparatus, dynamic reconfiguration support method, and computer product: An apparatus controls a circuit having rewritable processor elements and includes an acquiring unit that acquires information concerning a first task under execution by the circuit; a reading unit that, when the information concerning the first task is acquired, reads from a memory, a completion time of the first task;... Agent: Fujitsu Patent Center C/o Cpa Global

20100082944 - Multi-thread processor: In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread... Agent: Mcginn Intellectual Property Law Group, PLLC

20100082945 - Multi-thread processor and its hardware thread scheduling method: A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100082946 - Microcomputer and its instruction execution method: A microcomputer in accordance with an exemplary embodiment of the preset invention include an instruction decoder 14 that decodes a branch multiple instruction including a conditional branch instruction to be executed at a first execution stage and a first operation instruction to be executed at a second execution stage, and... Agent: Mcginn Intellectual Property Law Group, PLLC

20100082947 - Very-long instruction word architecture with multiple processing units: A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.... Agent: Goodwin Procter LLP Patent Administrator

20100082948 - Channel command word pre-fetching apparatus: In a CCW fetching section, for each input/output device being a control objective, a result prediction table in which prediction values of status values to be returned from an input/output device as execution results of CCW commands, is referred to. Then, based on the prediction values, commands being pre-fetching objectives... Agent: Greer, Burns & Crain

20100082949 - Apparatus, computer program product and associated methodology for video analytics: A processor and associated methodology employ a SIMD architecture and instruction set to efficiently perform video analytics operation on images. The processor contains a group of SIMD instructions used by the method to implement video analytic filters that avoid bit expansion of the pixels to be filtered. The filters hold... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100082950 - Dynamically reconfiguring platform settings: In one embodiment, a system may receive a pattern from an analysis engine, where the pattern includes information regarding a corrective action to be taken on a configuration setting of a processor, configure a performance monitor based on the pattern, collect performance monitoring information during program operation, analyze the information... Agent: Trop, Pruner & Hu, P.C.

20100082951 - Multi-threaded parallel processor methods and apparatus: A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/or data for a second context in a second... Agent: Joshua D. Isenberg Jdi Patent

20100082952 - Processor: When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 group. The data of the strand 0 and... Agent: Staas & Halsey LLP

20100082953 - Recovery apparatus for solving branch mis-prediction and method and central processing unit thereof: A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer... Agent: J C Patents

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