|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) March listing by industry category 03/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/25/2010 > patent applications in patent subcategories.
20100077176 - Method and apparatus for improved calculation of multiple dimension fast fourier transforms: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data... Agent: Volpe And Koenig, P.C. Dept. Amd
20100077177 - Multiple processor core vector morph coupling mechanism: One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to issue a first issue group of instructions to the first processor... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20100077178 - Method and apparatus for extending processing time in one pipeline stage: A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input... Agent: Dario B. Crosetto C/o 3-d Computing Inc.
20100077179 - Method and apparatus for coherent device initialization and access: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base... Agent: Intel Corporation C/o Cpa Global
20100077180 - Generating predicate values based on conditional data dependency in vector processors: Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100077181 - System and method for issuing load-dependent instructions in an issue queue in a processing unit of a data processing system: A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A... Agent: Dillon & Yudell LLP
20100077183 - Conditional data-dependency resolution in vector processors: Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100077182 - Generating stop indicators based on conditional data dependency in vector processors: Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100077184 - Method and apparatus for removing a pipeline bubble: One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20100077185 - Managing thread affinity on multi-core processors: Embodiments of the invention intelligently associate processes with core processors in a multi-core processor. The core processors are asymmetrical in that the core processors support different features or provide different resources. The features or resources are published by the core processors or otherwise identified (e.g., via a query). Responsive to... Agent: Microsoft Corporation
20100077186 - Processing apparatus, processing system, and computer readable medium: A processing apparatus includes: an execution unit; an execution request accept unit; a process instruction unit; an information leakage preventing process execution unit; a recording unit; and a transmission unit.... Agent: Sughrue-265550
20100077187 - System and method to execute a linear feedback-shift instruction: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further... Agent: Qualcomm Incorporated
20100077188 - Emergency file protection system for electronic devices: Disclosed is a method, system, and computer readable medium for completing critical write functions to a non-volatile memory (NVM) system within an electronic device upon experiencing a sudden or unexpected loss of the main power to the electronic device. A sudden loss of main external power is detected and determined... Agent: Williams Mullen03/18/2010 > patent applications in patent subcategories.
20100070738 - Flexible results pipeline for processing element: A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighbourhood connection register configured to receive data from and send data to other processing elements.... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100070739 - Multiprocessor system and control method thereof: A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If... Agent: Staas & Halsey LLP
20100070740 - System and method for dynamic dependence-based parallel execution of computer software: A method of dynamic parallelization in a multi-processor identifies potentially independent computational operations, such as functions and methods, with a serializer that assigns a computational operation to a serialization set and a processor based on assessment of the data that the computational operation will be accessing upon execution.... Agent: Wisconsin Alumni Research Foundation
20100070741 - Microprocessor with fused store address/store data microinstruction: A microprocessor includes an instruction translator that translates a store macroinstruction into exactly one fused store microinstruction. The store macroinstruction in the microprocessor's macroarchitecture macroinstruction set instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location. The fused store microinstruction is an... Agent: Huffman Law Group, P.C.
20100070742 - Embedded-dram dsp architecture having improved instruction set: An embedded-DRAM processor architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data... Agent: Fletcher Yoder (micron Technology, Inc.)03/11/2010 > patent applications in patent subcategories.
20100064115 - Vector processing unit: It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A vector processing apparatus has a plurality of register banks and processes a data string... Agent: Mr. Jackson Chen
20100064116 - Method and system for packet encryption: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
20100064117 - Apparatus and method for updating set of limited access model specific registers in a microprocessor: A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode... Agent: Huffman Law Group, P.C.
20100064118 - Method and apparatus for reducing latency associated with executing multiple instruction groups: A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed... Agent: Henneman & Associates, PLC
20100064119 - Data processor: The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for... Agent: Miles & Stockbridge PC
20100064120 - Replay reduction for power saving: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first... Agent: Mhkkg, PC/apple, Inc.
20100064121 - Dual-issuance of microprocessor instructions using dual dependency matrices: A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are... Agent: Leveque Intellectual Property Law, P.C.
20100064122 - Fast string moves: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register.... Agent: Huffman Law Group, P.C.
20100064123 - Hybrid branch prediction device with sparse and dense prediction caches: A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)03/04/2010 > patent applications in patent subcategories.
20100058029 - Invoking multi-library applications on a multiple processor system: A mechanism is provided for invoking a multi-library application on a multiple processor system, wherein the multiple processor system comprises a Power Processing Element (PPE) and a plurality of Synergistic Processing Element (SPE). Applications including multi-libraries run in the memory of the PPE. The mechanism comprises maintaining the status of... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100058030 - Arithmetic-logic unit, processor, and processor architecture: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a... Agent: Katten Muchin Rosenman LLP
20100058031 - Executing a service program for an accelerator application program in a hybrid computing environment: Executing a service program for an accelerator application program in a hybrid computing environment that includes a host computer and an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module; where the service program includes a host portion... Agent: Ibm (roc-blf)
20100058032 - Effective use of a bht in processor having variable length instruction set execution modes: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table... Agent: Qualcomm Incorporated
20100058034 - Creating register dependencies to model hazardous memory dependencies: A method of transforming low-level programming language code written for execution by a target processor includes receiving data comprising a plurality of low-level programming language instructions ordered for sequential execution by the target processor; detecting a pair of instructions in the plurality of low-level programming language instructions having a memory... Agent: Cantor Colburn LLP-ibm Europe
20100058033 - System and method for double-issue instructions using a dependency matrix and a side issue queue: A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.
20100058035 - System and method for double-issue instructions using a dependency matrix: A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.
20100058036 - Distributed acceleration devices management for streams processing: A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system. The available nodes and available acceleration devices in the computing system are identified. In addition, a plurality... Agent: George A. Willinghan, Iii August Law, LLC
20100058037 - Running-shift instructions for processing vectors: The described embodiments provide a processor for generating a result vector with shifted values. During operation, the processor receives a first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a key element position in the... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100058038 - Branch target buffer system and method for storing target address: A branch target buffer (BTB) system and method for storing target address is provided, applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When storing the target address of the branch instruction, the BTB stores the variation range, carry bit and sub/add bit of the target address without having... Agent: Lin & Associates Intellectual Property, Inc.
20100058039 - Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop... Agent: Hitt Gaines P.C.Previous industry: Electrical computers and digital processing systems: memory
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