|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
02/2010 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) February patent applications/inventions, industry category 02/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/25/2010 > patent applications in patent subcategories.
20100049941 - System and method for parallel processing using a type i howard cascade: A method using for performing a scatter-type data distribution among a cluster of computational devices. A number of nodes (equal to a value Cg, the number of tree generator channels) are initially generated, each connected to an initial generator, to create respective initial root nodes of an initial tree structure.... Agent: Lathrop & Gage LLP
20100049942 - Dragonfly processor interconnect network: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such... Agent: Schwegman, Lundberg & Woessner, P.A.
20100049943 - Programmable control pipeline architecture and pipeline processing system thereof: The present invention provides a control pipeline architecture and a pipeline processing system thereof, which is applicable to digital and analog integrated circuit (IC) design flow for convenient hardware implementation. In which, a closed loop control pipeline architecture includes a plurality of control units, and each of the control units... Agent: Bacon & Thomas, PLLC
20100049945 - Crypto-engine for cryptographic processing of data: A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic... Agent: Alix Yale & Ristas LLP
20100049946 - Processor, computer readable recording medium, and storage device: A processor includes: a first storage part that stores instructions of a program including sets of instruction groups, which sets are hierarchically structured; a second storage part that stores an address value of the first storage part in which an instruction to be read next is stored; a third storage... Agent: Greer, Burns & Crain
20100049947 - Processor and early-load method thereof: A processor and an early-load method thereof are provided. In the early-load method, an instruction is fetched and determined in an instruction fetch stage to obtain a determination result. Whether to early-load an early-loaded data corresponding to the instruction is determined according to the determination result. A target data is... Agent: J C Patents
20100049948 - Serial flash semiconductor memory: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential... Agent: Clise, Billion & Cyr, P.A.
20100049949 - Parallel program execution of command blocks using fixed backjump addresses: The invention relates to a method for executing instructions in a processor, according to which an instruction to be executed of a program memory is addressed by a program control unit by means of a program counter reading of a program counter that operates in said unit. The addressed instruction... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100049951 - Running-and, running-or, running-xor, and running-multiply instructions for processing vectors: The described embodiments provide a processor for generating a result vector with shifted values. During operation, the processor receives a first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a key element position in the... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100049950 - Running-sum instructions for processing vectors: The described embodiments provide a processor for generating a result vector with summed values from a first input vector. During operation, the processor receives the first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100049952 - Microprocessor that performs store forwarding based on comparison of hashed address bits: An apparatus for decreasing the likelihood of incorrectly forwarding store data includes a hash generator, which hashes J address bits to K hashed bits. The J address bits are a memory address specified by a load/store instruction, where K is an integer greater than zero and J is an integer... Agent: Huffman Law Group, P.C.
20100049953 - Data cache receive flop bypass: A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index... Agent: Townsend And Townsend And Crew LLP/mips
20100049954 - Method for speculative execution of instructions and a device having speculative execution capabilities: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding... Agent: Freescale Semiconductor, Inc. Law Department
20100049955 - Debug instruction for use in a multi-threaded data processing system: For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction... Agent: Freescale Semiconductor, Inc. Law Department
20100049956 - Debug instruction for use in a multi-threaded data processing system: For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug instruction by... Agent: Freescale Semiconductor, Inc. Law Department
20100049957 - Recovering a subordinate strand from a branch misprediction using state information from a primary strand: Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode.... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20100049958 - Method for executing an instruction loops and a device having instruction loop execution capabilities: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit... Agent: Freescale Semiconductor, Inc. Law Department02/18/2010 > patent applications in patent subcategories.
20100042806 - Determining index values for bits of a binary vector: In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M sub-vector index values, where each sub-vector index value corresponds to a different bit of a sub-vector of... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100042807 - Increment-propagate and decrement-propagate instructions for processing vectors: The described embodiments provide a processor for generating a result vector with incremented or decremented values from an input vector. During operation, the processor receives an input vector and a control vector. The processor then copies a value contained in a selected element of the input vector. The processor next... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100042808 - Provision of extended addressing modes in a single instruction multiple data (simd) data processor: Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a first register, wherein each register of the plurality of registers includes a main portion of N bits and an extension... Agent: Freescale Semiconductor, Inc. Law Department
20100042809 - Method and system for implementing a stream processing computer architecture: A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch... Agent: Cantor Colburn LLP-ibm Yorktown
20100042810 - Multiprocessor method and system using stacked processor modules and board-to-board connectors: A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor... Agent: Mindray C/o Stoel Rives LLP
20100042811 - Method for managing branch instructions and a device having branch instruction management capabilities: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages,... Agent: Freescale Semiconductor, Inc. Law Department
20100042812 - Data dependent instruction decode: A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20100042813 - Redundant execution of instructions in multistage execution pipeline during unused execution cycles: A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20100042814 - Extended instruction set architectures: An instruction set architecture includes a definition set of extended real values (e.g., computations or values that typically produce an IEEE NaN result) and a rules set of extended real value rules specifying values for one or more functions of one or more extended real values. Operations are performed on... Agent: Hewlett-packard Company Intellectual Property Administration
20100042816 - Break, pre-break, and remaining instructions for processing vectors: The described embodiments provide a system that sets elements in a result vector based on an input vector. During operation, the system determines a location of a key element within the input vector. Next, the system generates a result vector. When generating the result vector, the system sets one or... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100042818 - Copy-propagate, propagate-post, and propagate-prior instructions for processing vectors: The described embodiments provide a processor for generating a result vector with copied or propagated values from an input vector. During operation, the processor receives at least one input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain copied propagated values from... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100042815 - Method and apparatus for executing program code: The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100042817 - Shift-in-right instructions for processing vectors: The described embodiments provide a processor for generating a result vector with shifted values from an input vector. During operation, the processor receives an input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain shifted values or propagated values from the input... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20100042819 - Computer readable medium, operation controlling method, and operation control system: A computer readable medium storing a program causing a computer to execute a process for controlling a plurality of operations, the process including: accepting a change request to change an operation result of an operation executed prior to a current execution-permitted operation which an execution is permitted based on an... Agent: Oliff & Berridge, PLC02/11/2010 > patent applications in patent subcategories.
20100037035 - Generating an executable version of an application using a distributed compiler operating on a plurality of compute nodes: Methods, apparatus, and products are disclosed for generating an executable version of an application using a distributed compiler operating on a plurality of compute nodes that include: receiving, by each compute node, a portion of source code for an application; compiling, in parallel by each compute node, the portion of... Agent: Ibm (roc-blf)
20100037037 - Method for instruction pipelining on irregular register files: A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and... Agent: Wpat, PC Intellectual Property Attorneys
20100037036 - Method to improve branch prediction latency: An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100037038 - Dynamic core pool management: Embodiments that dynamically manage core pools are disclosed. Various embodiments involve measuring the amount of a computational load on a computing device. One way of measuring the load may consist of executing a number of instructions, in a unit of time, with numerous cores of the computing device. These embodiments... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC
20100037039 - Instruction operation code generation system: It is possible to increase the processor instruction set design job efficiency and reduce workload on designers in investigation of an instruction set. An instruction operation code generation system includes an operation code bit width decision means, an instruction sorting means, and an operation code value decision means. The operation... Agent: Mr. Jackson Chen02/04/2010 > patent applications in patent subcategories.
20100031002 - Simd microprocessor and operation method: A disclosed SIMD microprocessor includes a processor element unit including multiple processor elements; and a global processor unit configured to interpret a program pre-recorded in a memory and supply a control signal to the processor element unit. Each of the processor elements includes an operational circuit; a first forwarding path... Agent: Dickstein Shapiro LLP
20100031003 - Method and apparatus for partitioning and sorting a data set on a multi-processor system: The present invention provides a method and apparatus for partitioning, sorting a data set on a multi-processor system. Herein, the multi-processor system has at least one core processor and a plurality of accelerators. The method for partitioning a data set comprises: partitioning iteratively said data set into a plurality of... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100031004 - Arithmetic device: Unit blocks are arranged in a matrix and adjacent unit blocks are coupled. For the unit blocks arranged in a matrix, serial block numbers are assigned so as to form a closed loop curve. In a boundary region of minimum dividable unit blocks, selectors are arranged at input ports of... Agent: Mcdermott Will & Emery LLP
20100031005 - Instruction encoding for system register bit set and clear: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20100031006 - Thread completion rate controlled scheduling: A method, processor and processing system provide management of per-thread pipeline resource allocation in a simultaneous multi-threaded (SMT) processor by counting indications of instruction completion for each of the threads. The indication may be the commit phase of the pipeline, which indicates results of the pipeline instruction execution are ready... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.
20100031007 - Method to accelerate null-terminated string operations: A method reads and compares first and second register values, each with a size of at least two bytes. A third register indicates a match if: (1) a byte in the first register value is equal to (or, alternatively, not equal to) a corresponding byte in the second register value,... Agent: Barnes & Thornburg LLP
20100031008 - Parallel sorting apparatus, method, and program: A parallel sorting apparatus is provided whose sorting processing is speeded up. A reference value calculation section calculates a plurality of reference values serving as boundaries of intervals used for allocating input data depending on the magnitude of a value. An input data aggregation section partitions the input data into... Agent: Mr. Jackson Chen
20100031009 - Floating point execution unit for calculating a one minus dot product value in a single pass: A floating point execution unit calculates a one minus dot product value in a single pass. As such, the dependency that otherwise would be required to perform the calculations is eliminated, resulting in a substantially faster performance of such calculations. The floating point execution unit may be used, for example,... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20100031010 - Branch target buffer allocation: A data processing system and method are provided for allocating an entry in a branch target buffer (BTB). The method comprises: receiving a branch instruction to be executed in a data processor; determining that the BTB does not include an entry corresponding to the branch instruction; identifying an entry in... Agent: Freescale Semiconductor, Inc. Law Department
20100031011 - Method and apparatus for optimized method of bht banking and multiple updates: The invention relates to a method and apparatus for controlling the instruction flow in a computer system and more particularly to the predicting of outcome of branch instructions using branch prediction arrays, such as BHTs. In an embodiment, the invention allows concurrent BHT read and write accesses without the need... Agent: Snell & Wilmer L.L.P. (ibm Corp)Previous industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.13541 seconds