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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) January recently filed with US Patent Office 01/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/28/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100023728 - Method and system for in-place multi-dimensional transpose for multi-core processors with software-managed memory hierarchy: A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number of equally sized portions in the local memory, in each processor performing... Agent: Ibm - Eu C/o Myers Andras Sherman LLP
20100023729 - Implementing signal processing cores as application specific processors: Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control path is implemented using processor components... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera
20100023730 - Circular register arrays of a computer: The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer 100 while remaining fully operational in case of single event upset caused by radiation and a method and apparatus for eliminating stack overflow and underflow by replacing a conventional stack with... Agent: Henneman & Associates, PLC
20100023731 - Generation of parallelized program based on program dependence graph: A method of generating a parallelized program includes calculating an execution order of vertices of a degenerate program dependence graph, generating basic blocks by consolidating vertices including neither branching nor merging, generating procedures each corresponding to a respective one of the vertices, and generating a procedure control program by arranging... Agent: Staas & Halsey LLP
20100023732 - Optimizing non-preemptible read-copy update for low-power usage by avoiding unnecessary wakeups: A technique for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers. A grace period processing action is implemented that requires a processor that may be running a non-preemptible reader of the shared data element to pass through a quiescent state... Agent: Walter W. Duft
20100023733 - Microprocessor extended instruction set precision mode: A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits... Agent: Henneman & Associates, PLC
20100023734 - System, method and computer program product for executing a high level programming language conditional statement: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits... Agent: Freescale Semiconductor, Inc. Law Department
20100023735 - Debug message generation using a selected address type: A method for generating a debug message includes receiving a translated address and an untranslated address associated with a same processor operation, determining a value of one or more control indicators, selecting the translated address or the untranslated address as a selected address based on the value of the one... Agent: Freescale Semiconductor, Inc. Law Department
20100023736 - Reconfigurable circuit, reset method, and configuration information generation device: The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation... Agent: Wenderoth, Lind & Ponack L.L.P.01/21/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100017579 - Program-controlled unit and method for operating same: A method for operating a program-controlled unit has two redundantly operable microprocessor cores and a comparator unit provided downstream from the two microprocessor cores. One working register having a different content is provided in each of the two microprocessor cores for the redundant operation, and the content of these working... Agent: Kenyon & Kenyon LLP
20100017580 - Pre-decode checking for pre-decoded instructions that cross cache line boundaries: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a... Agent: Nixon & Vanderhye P.C.
20100017581 - Low overhead atomic memory operations: Embodiments that provide low-overhead restricted memory transactions are disclosed. In accordance with one embodiment, the method includes providing one or more references to processor-specific data that corresponds to a first processor. The method further includes detecting an interrupt to the first processor when the interrupt indicates modification of the one... Agent: Lee & Hayes, PLLC
20100017582 - Stall prediction thread management: Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the identified instructions are likely, thread switching instructions are added to the first thread in place of the identified instructions. Thread switching instructions direct... Agent: Townsend And Townsend And Crew, LLP
20100017583 - Call stack sampling for a multi-processor system: A computer implemented method, apparatus, and computer usable program code for sampling call stack information. Responsive to identifying an interrupt, a determination is made as to whether all processors in a plurality of processors have generated the interrupt. A determination is made as whether to sample the call stack information... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20100017584 - Call stack sampling for a multi-processor system: A computer implemented method for sampling call stack information. Responsive to identifying a set of interrupts, a determination is made as to whether all processors in a plurality of processors have generated the set of interrupts. A number of addresses are identified for a set of interrupted threads identified by... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20100017585 - Microcomputer and encoding system for instruction code and cpu: A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral... Agent: Posz Law Group, PLC
20100017586 - Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction... Agent: Stmicroelectronics, Inc.01/14/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100011189 - Information processing device and method for designing an information processing device: An information processing device includes a plurality of processor cores each including a plurality of transistors, and at least one substrate bias circuit that supplies each of the plurality of transistors with a substrate bias voltage that is determined based on the number of the processor cores.... Agent: Staas & Halsey LLP
20100011190 - Decoding multithreaded instructions: A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of... Agent: Dorsey & Whitney LLP On Behalf Of Sun Microsystems, Inc.
20100011191 - Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor: A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from... Agent: Mcdermott Will & Emery LLP
20100011193 - Selective hardware lock disabling: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire... Agent: Trop, Pruner & Hu, P.C.
20100011192 - Simplifying complex data stream problems involving feature extraction from noisy data: Methods, systems and computer program products for simplifying complex data stream problems involving feature extraction from noisy data. Exemplary embodiments include a method for processing a data stream, including applying multiple operators to the data stream, wherein an operation by each of the multiple operators includes retrieving the next chunk... Agent: Cantor Colburn, LLP - IBM Arc Division
20100011194 - State as a first-class citizen of an imperative language: A state component saves a present state of a program or model. This state component can be invoked by the program or model itself, thereby making state a first-class citizen. As the state of the program evolves from the saved state, the saved state remains for reflection and recall, for... Agent: Klarquist Sparkman LLP
20100011195 - Processor: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more... Agent: Wolf Greenfield & Sacks, P.C.
20100011196 - Method and program network for exception handling: A method and a program network for exception handling are described. At least one error program element including an input and an output and an item of exception information stored for exception handling in the form of a data structure are defined in a graphical programming language.... Agent: Siemens Corporation Intellectual Property Department01/07/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100005273 - Method for selecting node in network system and system thereof: The present invention relates to a method for selecting a node in a network system and a system thereof. The method performs a writing operation on a majority of the nodes included in at least one cell selected by dividing a network area including a plurality of nodes existing on... Agent: Lowe Hauptman Ham & Berner, LLP
20100005275 - Multiprocessing system: A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task... Agent: Staas & Halsey LLP
20100005274 - Virtual functional units for vliw processors: A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100005276 - Information processing device and method of controlling instruction fetch: An information processing device includes an instruction fetch unit, an instruction buffer, an instruction executing unit, and an instruction fetch control unit. The instruction fetch unit supplies a fetch address to an instruction memory. The instruction buffer stores an instruction read out from the instruction memory. The instruction executing unit... Agent: Sughrue Mion, PLLC
20100005277 - Communicating between multiple threads in a processor: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a... Agent: Trop, Pruner & Hu, P.C.
20100005278 - Device and method for controlling an internal state of information processing equipment: The state control device for controlling an internal state of information processing equipment includes a scenario table, an information recorder, an information player and a state change controller. The information recorder acquires sync information and one item or a plurality of items of state information from the information processing equipment... Agent: Mcdermott Will & Emery LLP
20100005279 - Data processor: The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical functions as an integrated whole of processors (CPU1 and CPU2)... Agent: Stanley P. Fisher Reed Smith LLPPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
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