Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) December patent applications/inventions, industry category 12/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
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12/31/2009 > patent applications in patent subcategories.

20090327651 - Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and... Agent: Mark P. Kahler

20090327652 - Method for constructing a variable bitwidth video processor: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each... Agent: Myers Wolin, LLC

20090327653 - Reconfigurable computing circuit: A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig... Agent: Wenderoth, Lind & Ponack L.L.P.

20090327654 - Method of handling duplicate or invalid node controller ids in a distributed service processor environment: A method for enabling a Node Controller (NC), which claims a duplicate or invalid service processor Node Controller Identification (NCID) in a distributed service processor system, to be integrated into the system includes reading an NCID by the NC after the NC is booted, saving the NCID into a non-volatile... Agent: Mcginn Intellectual Property Law Group, PLLC

20090327655 - Semiconductor device and data processing method performed by semiconductor device: The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the... Agent: Turocy & Watson, LLP

20090327656 - Efficiency-based determination of operational characteristics: Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core)... Agent: Kacvinsky LLC C/o Intellevate

20090327658 - Compare, swap and store facility with no external serialization: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090327657 - Generating and performing dependency controlled flow comprising multiple micro-operations (uops): A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090327659 - Trap-based mechanism for tracking memory accesses: In general, the invention relates to a method. The method includes receiving notification, which includes context information, of a trap. The method further includes accessing, based at least partially upon the context information, a particular instruction that caused the trap, determining, based at least partially upon the context information, a... Agent: Osha Liang L.L.P./sun

20090327660 - Memory throughput increase via fine granularity of precharge management: Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments... Agent: Caven & Aghevli LLC C/o Cpa Global

20090327662 - Managing active thread dependencies in graphics processing: A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be executed before the first thread's execution. Thread execution may be freely reordered, subject only to the... Agent: Trop, Pruner & Hu, P.C.

20090327661 - Mechanisms to handle free physical register identifiers for smt out-of-order processors: Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers... Agent: Caven & Aghevli LLC C/o Cpa Global

20090327663 - Power aware retirement: In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated... Agent: Trop, Pruner & Hu, P.C.

20090327664 - Arithmetic processing apparatus: An arithmetic processing apparatus includes an operation circuit group that performs encryption and a redundant operation circuit group configured the same as the operation circuit group. The arithmetic processing apparatus, while performing encryption, performs normal encryption in the operation circuit group, and performs an encryption mask processing program by using... Agent: Staas & Halsey LLP

20090327665 - Efficient parallel floating point exception handling in a processor: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the... Agent: Trop, Pruner & Hu, P.C.

20090327666 - Method and system for hardware-based security of object references: A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data... Agent: Osha Liang L.L.P./sun

20090327668 - Multi-threaded processes for opening and saving documents: Tools and techniques are described for multi-threaded processing for opening and saving documents. These tools may provide load processes for reading documents from storage devices, and for loading the documents into applications. These tools may spawn a load process thread for executing a given load process on a first processing... Agent: Microsoft Corporation

20090327667 - System and method to perform fast rotation operations: Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set... Agent: Qualcomm Incorporated

20090327669 - Information processing apparatus, program execution method, and storage medium: According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090327671 - Processor resource management: Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions... Agent: Constellation Law Group, PLLC

20090327670 - Variable length stages in a pipeline: A circuit having a pipeline and a configuration circuit. The pipeline generally has multiple stages linked in series by registers. The registers may be governed by a clock signal having a first frequency in a first mode and a second frequency in a second mode. The second frequency may be... Agent: Christopher P Maiorana, PC Lsi Corporation

20090327672 - Secured processing unit: A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by the processing unit. The method may... Agent: Seed Intellectual Property Law Group PLLC

20090327673 - Estimator, table managing device, selecting device, table managing method, program for allowing computer to execute the table managing method, and recording medium where the program is recorded: An estimator suitable for hot-path detection conducted while managing the history of the executed instructions is provided. A hot-path estimator (1) comprises a table in which branch instruction specifying information for specifying a branch instruction, the branch destination address of each executed branch instruction, the number of branches, and execution... Agent: Turocy & Watson, LLP

20090327674 - Loop control system and method: Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to... Agent: Qualcomm Incorporated

12/24/2009 > patent applications in patent subcategories.

20090319754 - Reconfigurable device: A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls... Agent: Mcginn Intellectual Property Law Group, PLLC

20090319755 - Method and apparatus for high speed data stream splitter on an array of processors: A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors 305(da), which splits off a substream and passes the data stream onto a second processor... Agent: Henneman & Associates, PLC

20090319756 - Duplexed operation processor control system, and duplexed operation processor control method: The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor... Agent: Juan Carlos Marquez Reed Smith LLP

20090319757 - Architecture for local programming of quantum processor elements using latching qubits: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with... Agent: Seed Intellectual Property Law Group PLLC

20090319758 - Processor, performance profiling apparatus, performance profiling method , and computer product: A processor capable of executing an arbitrary application program on an operating system includes an event context register that stores therein an ID of an event to be measured in the arbitrary application program and a context register that records therein an ID of an event executed by the arbitrary... Agent: Staas & Halsey LLP

20090319759 - Seamless frequency sequestering: A method and apparatus for seamless frequency sequestering is herein described. In response to a frequency throttle event, controlling software, such as an OS, is provided access to a throttled amount of frequency associated with the frequency throttle event, while another amount of frequency is transparently sequestered for performance of... Agent: Intel Corporation C/o Cpa Global

20090319760 - Single-cycle low power cpu architecture: An n architecture for implementing an instruction pipeline within a CPU comprises an arithmetic logic unit (ALU), an address arithmetic unit (AAU), a program counter (PC), a read-only memory (ROM) coupled to the program counter, to an instruction register, and to an instruction decoder coupled to the arithmetic logic unit.... Agent: Schwegman, Lundberg & Woessner / Atmel

20090319761 - Hardware constrained software execution: Restricting execution by a computing device of instructions within an application program. The application program is modified such that execution of the selected instructions is dependent upon a corresponding expected state of one or more hardware components in the computing device. In an embodiment, the application program is modified to... Agent: Microsoft Corporation Patent Group Docketing Dept.

20090319762 - Dynamic reconfigurable circuit and data transmission control method: A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A... Agent: Arent Fox LLP

12/17/2009 > patent applications in patent subcategories.

20090313454 - Multiprocessor system and display device using the same: In a multiprocessor system (1), a processor (3) as a monitor monitors data read access performed by a processor (2) as a master to a memory (4) as a slave. The processor (3) acquires data outputted from the memory (4) when a data read-out command outputted from the processor (2)... Agent: Harness, Dickey & Pierce, P.L.C

20090313455 - Instruction issue control wtihin a multithreaded processor: A multithreaded processor is provided with a saturating counter which serves to generate a thread preference signal to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter is updated based upon the selections made for issue. The counter is a... Agent: Nixon & Vanderhye, PC

20090313456 - Methods and apparatus for dynamic prediction by software: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20090313457 - System and method for extracting fields from packets having fields spread over more than one register: Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090313458 - Method and apparatus for vector execution on a scalar machine: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090313459 - System and method for processing low density parity check codes using a deterministic caching apparatus: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090313460 - Trace compression method for debug and trace interface of microprocessor: The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the... Agent: Wpat, PC Intellectual Property Attorneys

20090313461 - Circuit with a plurality of modes of operation: A circuit capable of being operated in a first and a second mode of operation comprises a storage location adapted to store at least a first state, a second state and a third state, wherein the circuit is adapted to switch to the first mode of operation when the storage... Agent: Dickstein Shapiro LLP

20090313462 - Methods involving branch prediction: A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location data location, and saving the data in a branch prediction memory.... Agent: Cantor Colburn LLP-ibm Yorktown

12/10/2009 > patent applications in patent subcategories.

20090307463 - Inter-processor, communication system, processor, inter-processor communication method, and communication method: An inter-processor communication system includes processors and a transfer device that, upon receiving a multicast packet from any of the processors, transfers the packet to processors designated in the packet as destinations among the processors. Each processor includes: a memory unit; a holding unit which holds position information indicating a... Agent: Sughrue Mion, PLLC

20090307464 - System and method for parallel video processing in multicore devices: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual... Agent: Hamilton & Terrile, LLP - Freescale

20090307465 - Computational expansion system: The invention relates to a system for expanding capacity for executing processes that are executed in a central processing unit (12) which can be connected to a computational expansion means (11) comprising a task management means (32) which, by means of an internal management means (53), receives a request to... Agent: Ladas & Parry LLP

20090307466 - Resource sharing techniques in a parallel processing computing system: A method, apparatus, and program product share a resource in a computing system that includes a plurality of computing cores. A request from a second execution context (“EC”) to lock the resource currently locked by a first EC on a first core causes replication of the second EC as a... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090307467 - Performing an allreduce operation on a plurality of compute nodes of a parallel computer: Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer. Each compute node includes at least two processing cores. Each processing core has contribution data for the allreduce operation. Performing an allreduce operation on a plurality of compute nodes... Agent: Ibm (roc-blf)

20090307468 - Generating a test case micro generator during processor design verification and validation: A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation information, instruction sequences, base register available, target real memory pages, etc. In turn, the micro generator tests a processor using the initial test... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090307469 - Register set used in multithreaded parallel processor architecture: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows... Agent: Fish & Richardson, PC

20090307471 - Methods, systems and computer program products for fault tolerant applications: Methods, systems and computer program products for architecting fault tolerant applications. Embodiments of the invention include a method for executing an application in a computer system, the method including monitoring a behavior of the computer system, the computer system having a subsystem in an operating system of the computer system,... Agent: Ibm Corporation Intellectual Property Law

20090307470 - Multi thread processor having dynamic reconfiguration logic circuit: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures... Agent: Wenderoth, Lind & Ponack L.L.P.

20090307472 - Method and apparatus for nested instruction looping using implicit predicates: A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer... Agent: Motorola, Inc.

20090307473 - Method for adopting sequential processing from a parallel processing architecture: Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and... Agent: Emulex Design & Manufacturing Corporation C/o Morrison & Foerster LLP

12/03/2009 > 18 patent applications in 14 patent subcategories.

20090300323 - Vector processor system: A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In... Agent: West & Associates, A PC

20090300324 - Array type processor and data processing system: In data path means, processor elements individually execute data processing in accordance with command codes described in a computer program, and switching elements individually control a connection relationship to switch among a plurality of processor elements in accordance with the command codes. When an access to an external memory is... Agent: Foley And Lardner LLP Suite 500

20090300325 - Data processing system, apparatus and method for performing fractional multiply operations: A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs... Agent: Oliff & Berridge, PLC

20090300326 - System, method and computer program for transforming an existing complex data structure to another complex data structure: A method (system and computer program product) performs facet classification synthesis to relate concepts represented by concept definitions defined in accordance with a faceted data set comprising facets, facet attributes, and facet attributes hierarchies. Dimensional concept relationships are expressed between the concept definitions. Two concept definitions are determined to be... Agent: Miller Thompson, LLP

20090300327 - Execution engine: The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. Possible applications include many types of digital signal processing computations, such as filtering, convolution, and deconvolution, as well as many types of linear algebra operators, such as... Agent: Haverstock & Owens LLP

20090300328 - Aligning protocol data units: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing... Agent: Baker Botts L.L.P.

20090300330 - Data processing method and system based on pipeline: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index,... Agent: Ibm Corporation (swp)

20090300329 - Voltage droop mitigation through instruction issue throttling: A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090300331 - Implementing instruction set architectures with non-contiguous register file specifiers: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous... Agent: Keusey, Tutunjian A Bitetfo, P.C.

20090300333 - Hardware support for work queue management: The claimed matter provides systems and/or methods that effectuate utilization of fine-grained concurrency in parallel processing and efficient management of established memory structures. The system can include devices that establish memory structures associated with individual processors that can comprise a parallel processing phalanx. The system can thereafter utilize various enqueuing... Agent: Microsoft Corporation

20090300334 - Method and apparatus for loading data and instructions into a computer: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC

20090300332 - Non-destructive sideband reading of processor state information: A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary... Agent: Zagorin O'brien Graham LLP (151)

20090300335 - Execution unit with inline pseudorandom number generator: A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090300336 - Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program... Agent: Rines & Rines

20090300337 - Instruction set design, control and communication in programmable microprocessor cases and the like: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit... Agent: Rines & Rines

20090300338 - Aggressive store merging in a processor that supports checkpointing: Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090300339 - Lsi for ic card: To prevent exposure or tampering of data by an illegal access to a memory of an LSI, a ROM (13) has two separate program regions corresponding to memory access authorities. Only when detecting a branch instruction generating signal from a CPU (12), an address decoding circuit (23) decodes a branch... Agent: Mcdermott Will & Emery LLP

20090300340 - Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection: A method for prefetching data and/or instructions from a main memory to a cache memory may include generating control flow information by storing respective information for each retired branch instruction. The method may further include storing respective one or more cache miss addresses for each retired instruction that incurs one... Agent: Mhkkg/sun

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