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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) November recently filed with US Patent Office 11/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
11/26/2009 > 9 patent applications in 8 patent subcategories. recently filed with US Patent Office

20090292900 - Multiprocessor node control tree: Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other... Agent: Schwegman, Lundberg & Woessner, P.A.

20090292901 - Microprocessor apparatus and method for persistent enablement of a secure execution mode: An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed exclusively within a secure execution mode within the microprocessor. The non-secure application programs are accessed from a... Agent: Huffman Law Group, P.C.

20090292902 - Apparatus and method for managing a microprocessor providing for a secure execution mode: An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus. The secure application program executes in a secure execution... Agent: Huffman Law Group, P.C.

20090292903 - Microprocessor providing isolated timers and counters for execution of secure code: An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The a microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus.... Agent: Huffman Law Group, P.C.

20090292904 - Apparatus and method for disabling a microprocessor that provides for a secure execution mode: An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed... Agent: Huffman Law Group, P.C.

20090292905 - Performing an allreduce operation on a plurality of compute nodes of a parallel computer: Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer, each node including at least two processing cores, that include: performing, for each node, a local reduction operation using allreduce contribution data for the cores of that node, yielding,... Agent: Ibm (roc-blf)

20090292906 - Multi-mode register file for use in branch prediction: A multi-mode register file is described. In one embodiment, the multi-mode register file includes an operand in a first mode. The multi-mode register file further includes auxiliary information which replaces the operand in a second mode.... Agent: Qualcomm Incorporated

20090292907 - Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090292908 - Method and arrangements for multipath instruction processing: A system is disclosed that includes a fetch stage to retrieve an instruction to be utilized by processing units in a multi-path pipeline. The instruction can have selectors that can select functions to be performed by individual paths of the pipeline that can accept and utilize the same instruction. A... Agent: Alan Carlson

  
11/19/2009 > 9 patent applications in 8 patent subcategories. recently filed with US Patent Office

20090287905 - Processor pipeline architecture logic state retention systems and methods: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of... Agent: Hoffman Warnick LLC

20090287906 - Allocating resources to partitions in a partitionable computer: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies... Agent: Hewlett-packard Company Intellectual Property Administration

20090287907 - System for providing trace data in a data processor having a pipelined architecture: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the... Agent: Flynn Thiel Boutell & Tanis, P.C.

20090287908 - Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20090287909 - Dynamically estimating lifetime of a semiconductor device: In one embodiment, the present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating... Agent: Trop, Pruner & Hu, P.C.

20090287910 - System and method for providing preprogrammed imaging in a data collection environment: In more specific embodiments, the instructions are triggered when the imaging device is powered ON. The instructions can verify the first connection to the hard-drive and the second connection to the output capture device. The instructions can include a template that reflects a loaded routine for imaging the hard-drive based... Agent: Patent Capital Group

20090287911 - Programmable signal and processing circuit and method of depuncturing: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric... Agent: Leydig Voit & Mayer, Ltd

20090287912 - System and method for branch misprediction using complementary branch predictions: A system is disclosed for providing branch misprediction prediction in a microprocessor. The system includes a mispredicted branch table that includes address, distance, and true/not true fields, and an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3)... Agent: Gauthier & Connors, LLP

  
11/12/2009 > 9 patent applications in 8 patent subcategories. recently filed with US Patent Office
  
11/05/2009 > 9 patent applications in 8 patent subcategories. recently filed with US Patent Office

20090276606 - Method and system for parallel histogram calculation in a simd and vliw processor: The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where the SIMD processor could perform N LUT operations... Agent: Sawyer Law Group PC

20090276607 - Virtualization platform with dedicated cache access: A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls... Agent: Hewlett-packard Company Intellectual Property Administration

20090276608 - Micro processor, method for encoding bit vector, and method for generating bit vector: In a microprocessor for pipeline processing instruction execution, dependency relationship information representing a dependency relationship of each of a plurality of instructions with all the preceding instructions is stored, and whether or not the instructions in stages after instruction issue depend on the instruction of a miss speculation is judged... Agent: Gerald E. Hespos Casella & Hespos LLP

20090276609 - Configurable pipeline based on error detection mode in a data processing system: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor... Agent: Freescale Semiconductor, Inc. Law Department

20090276610 - Test case generation with backward propagation of predefined results and operand dependencies: A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090276611 - Ram block branch history table in a global history branch prediction system: Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of... Agent: Gerald W. Maliszewski

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