|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) October categorized by USPTO classification 10/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/30/2009 > patent applications in patent subcategories.
10/23/2009 > patent applications in patent subcategories.
10/15/2009 > patent applications in patent subcategories.
20090259823 - Circuit and design structure for a streaming digital data filter: A circuit and design structure for a streaming digital data filter embodied in a machine readable medium, the design structure including: a data processing unit and a pointer processing unit, the data processing unit and the pointer unit connected to a control logic; the pointer processing unit consisting of n... Agent: Schmeiser, Olsen & Watts
20090259822 - Streaming digital data filter: A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first... Agent: Schmeiser, Olsen & Watts
20090259824 - Reconfigurable integrated circuit: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated... Agent: Dennison, Schultz & Macdonald
20090259825 - Multi-core processing system: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet... Agent: Freescale Semiconductor, Inc. Law Department
20090259826 - Microprocessor extended instruction set mode: Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits... Agent: Henneman & Associates, PLC
20090259827 - System, method, and computer program product for creating dependencies amongst instructions using tags: A system, method, and computer program product are provided for creating dependencies amongst instructions using tags. In operation, tags are associated with a first instruction and a second instruction. Additionally, a dependency is created between the first instruction and the second instruction, utilizing the tags. Furthermore, the first instruction and... Agent: Zilka-kotab, PC- Rmi
20090259828 - Execution of retargetted graphics processor accelerated code by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.
20090259829 - Thread-local memory reference promotion for translating cuda code for execution by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.
20090259831 - Defining memory indifferent trace handles: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20090259830 - Quantifying completion stalls using instruction sampling: A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath,... Agent: Ibm Corp. (mrn) C/o Law Office Of Michael R. Nichols
20090259832 - Retargetting an application program for execution by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.10/08/2009 > patent applications in patent subcategories.
20090254734 - Partial load/store forward prediction: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality... Agent: Mhkkg, PC/apple, Inc.
20090254735 - Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture: A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and... Agent: Huffman Law Group, P.C.
20090254736 - Data processing system for performing data rearrangement operations: An apparatus for processing data is provided comprising rearrangement circuitry having a plurality of rearrangement stages for rearranging a plurality N of input data elements, each rearrangement stage comprising at most N multiplexers arranged to select between M data elements where M is in integer less than N. Control circuitry... Agent: Nixon & Vanderhye, PC
20090254737 - Information processing device, information processing supporting server and information processing system: In information processing device or the like is provided to output a suitable form of information from a view point of user's non-feeling of trouble. In the information processing system, whether a user issues an output instruction or not is confirmed only with respect to information that is not extracted... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000
20090254738 - Obfuscation device, processing device, method, program, and integrated circuit thereof: It is an object of the present invention to provide an obfuscation device that can achieve both sufficient obfuscation and the appropriate instruction block to be executed. In the obfuscation device, a first instruction generating unit, for each of the first process and the second process, generates an initialization instruction... Agent: Wenderoth, Lind & Ponack L.L.P.
20090254739 - Information processing device: An information processing device having a function for efficiently debugging a parallel processing program by controlling snoop operation is provided. The information processing device is so configured that the following is implemented: the setting for receiving a snoop request from a central processing unit can be set at a snoop... Agent: Miles & Stockbridge PC
20090254740 - Information processing device, encryption method of instruction code, and decryption method of encrypted instruction code: It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output... Agent: Miles & Stockbridge PC10/01/2009 > patent applications in patent subcategories.
20090249025 - Serial data processing circuit: A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets supplied to a logic circuit. These latch units sequentially latch the data sets sequentially supplied to the logic circuit and... Agent: Katten Muchin Rosenman LLP
20090249026 - Vector instructions to enable efficient synchronization and parallel reduction operations: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector... Agent: Trop, Pruner & Hu, P.c.
20090249027 - Method and apparatus for scrambling sequence generation in a communication system: A wireless communications method is provided. The method includes employing a processor executing computer executable instructions stored on a computer readable storage medium to implement various acts. The method also includes generating cyclic shifts for a sequence generator by masking shift register output values with one or more vectors. The... Agent: Qualcomm Incorporated
20090249028 - Processor with internal raster of execution units: The present invention relates to a processor that, as its main feature, has an internal raster of ALUs, with the help of which sequential programs are executed. The connections between the ALUs are automatically created at runtime dynamically by means of multiplexers. A central decoding and configuration unit that creates... Agent: Venable LLP
20090249029 - Method for ad-hoc parallel processing in a distributed environment: An overall processing time to rasterize, at the first device, the electronic document to be rendered is computed. Also, a rendering time to render, at the first device, the electronic document to be rendered is computed. When the overall processing time to rasterize at the first device is greater than... Agent: Basch & Nickerson LLP
20090249030 - Multiprocessor system having direct transfer function for program status information in multilink architecture: A multiprocessor system can directly transmit storage-state information in a multilink architecture. The multiprocessor system includes a first processor; a multiport semiconductor memory device coupled to the first processor; a nonvolatile semiconductor memory device; and a second processor coupled with the multiport semiconductor memory device and the nonvolatile semiconductor memory... Agent: F. Chau & Associates, Llc
20090249031 - Information processing apparatus and error processing: An information processing apparatus includes a first processing unit, a second processing unit, and a common storage unit that is commonly accessed by the first processing unit and the second processing unit. The first processing unit writes a request in the common storage unit for requesting the second processing unit... Agent: Staas & Halsey LLP
20090249032 - Information apparatus: An information apparatus comprises: a barrel shifter composed of a bidirectional 1-bit shifter, . . . , and a bidirectional 24-bit shifter which are connected in series; a control unit for outputting an endian conversion control signal SE indicating one of a shift operation and endian conversion; an endian conversion... Agent: Steptoe & Johnson LLP
20090249033 - Data processing apparatus and method for handling instructions to be executed by processing circuitry: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation... Agent: Nixon & Vanderhye P.c.
20090249034 - Processor and signature generation method, and multiple system and multiple execution verification method: A processor performs instruction execution regardless of a program order. An execution unit executes an instruction, and transmits end information of the instruction whose execution has ended. A retire unit receives the end information, rearranges a result of the instruction whose execution has ended in a program order to determine... Agent: Staas & Halsey LLP
20090249035 - Multi-cycle register file bypass: A method of reducing latency in instruction processing in a system, includes calculating a result of a first execution unit, storing the result of the first execution unit in a register file, forwarding the result of the first execution unit, through the bypass unit, to a second execution unit, the... Agent: Mcginn Intellectual Property Law Group, Pllc
20090249036 - Efficient method and apparatus for employing a micro-op cache in a processor: Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache... Agent: Larry Mennemeier Intel Corporation
20090249037 - Pipeline processors: A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of different complexity. A plurality of pipelines for executing instructions are provided and an instruction scheduler determines on each clock cycle the pipelines upon... Agent: Flynn Thiel Boutell & Tanis, P.c.
20090249038 - Stream data processing apparatus: In a normal operation state, a connection management section writes data transmitted from a first processing section to a data temporary storage section and reads data to be received by a second processing section from the data temporary storage section. Upon receiving control signals which instruct a change of the... Agent: Wenderoth, Lind & Ponack L.l.p.
20090249039 - Providing extended precision in simd vector arithmetic operations: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090249040 - Embedded control system: According to an embedded control system in the present invention, when discrete data in the floating-point format is stored in a read-only memory, the discrete data in the floating-point format is converted into data in a significand-reduced floating-point format before being stored. Here, a significand-reduced floating-point number is a number... Agent: Crowell & Moring LLP Intellectual Property Group
20090249041 - System and method for reducing power consumption in a device using register files: A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090249042 - Gateway apparatus, control instruction processing method, and program: A gateway apparatus includes a translator connected to a first network for one or more controllers to control one or more devices, and one or more aggregators. The translator includes an acquisition unit which acquires load information concerning a load on each of the controllers, a control instruction reception unit... Agent: Ohlandt, Greeley Ruggiero & Perle, L.l.p
20090249043 - Apparatus, method and computer program for processing instruction: A plurality of instructions to be executed in an order of being issued without an appointment of a waiting time or a starting moment are designed to be executed after a certain waiting time; instructions to be executed in an order of being issued without designation of starting moment or... Agent: Oliff & Berridge, Plc
20090249045 - Apparatus and method for condensing trace information in a multi-processor system: A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with... Agent: Mips C/o Cooley Godward Kronish LLP
20090249046 - Apparatus and method for low overhead correlation of multi-processor trace information: A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of... Agent: Mips C/o Cooley Godward Kronish LLP
20090249044 - Apparatus for and method for life-time test coverage for executable code: a novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for... Agent: Ibm Corporation, T.j. Watson Research Center
20090249047 - Method and system for relative multiple-target branch instruction execution in a processor: A method and system for relative multiple-target branch instruction execution in a processor is provided. One implementation involves receiving an instruction for execution; determining a next instruction to execute based on multiple condition bits or outcomes of a comparison by the current instruction; obtaining a specified instruction offset in the... Agent: Ibm-acc-washington C/o Myers Dawes Andras & Sherman, LLP
20090249048 - Branch target buffer addressing in a data processor: A data processing system includes a branch target buffer (BTB) including a plurality of entries, each entry comprising a tag portion and a long branch indicator. The system also includes segment target address storage circuitry which stores a plurality of segment target addresses, index storage circuitry which stores a plurality... Agent: Freescale Semiconductor, Inc. Law Department
20090249049 - Precise branch counting in virtualization systems: A method for precisely counting guest branch instructions in a virtualized computer system is described. In one embodiment, guest instructions execute in a direct execution mode of the virtualized computer system. The direct execution mode operates at a first privilege level having a lower privilege than a second privilege level.... Agent: Vmware, Inc.Previous industry: Electrical computers and digital processing systems: memory
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