|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All |
09/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) September class, title,number 09/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/24/2009 > patent applications in patent subcategories. class, title,number
20090240914 - Recycling long multi-operand instructions: A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240915 - Broadcasting collective operation contributions throughout a parallel computer: Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting... Agent: Ibm (roc-blf)
20090240916 - Fault resilient/fault tolerant computing: A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on... Agent: Fish & Richardson P.C.
20090240917 - Method and apparatus for matrix decomposition in programmable logic devices: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks... Agent: Townsend And Townsend And Crew LLP/ 015114
20090240918 - Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty: Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240919 - Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass: A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240920 - Execution unit with data dependent conditional write instructions: An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090240923 - Computing device with entry authentication into trusted execution environment and method therefor: A computing device (10) includes a trusted execution environment (TEE) manager (40) that manages a switchover from non-trusted software (116) to trusted software (118). The TEE manager (40) includes memory (90) configured to store password-bearing, immediate-operand instructions (54). At the point of switching between the non-trusted software (116) and the... Agent: Meschkow & Gresham, P.L.C
20090240924 - Information processing device, information processing method, and computer product: An information processing device disclosed includes a plurality of executing units for executing various processes. The information processing device and method thereof acquire setting information that indicates an operating condition with respect to each executing unit from information an operation of a main process executed by the plurality of executing... Agent: Staas & Halsey LLP
20090240921 - Method, system and computer program product for supporting partial recycle in a pipelined microprocessor: A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240922 - Method, system, computer program product, and hardware product for implementing result forwarding between differently sized operands in a superscalar processor: Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240926 - Arithmetic operating apparatus and method for performing arithmetic operation: A technique realizes execution of various combinations of arithmetic operations in, for example SIMD floating-point multiply-add arithmetic operation, with less instruction kind codes. An arithmetic operating apparatus includes a setting unit that sets in one or more unused bits of a single instruction extended instruction information to instruct at least... Agent: Staas & Halsey LLP
20090240925 - Device, method, and computer program product that process message: A first arithmetic unit performs a network process for transmission and reception of a message. A second arithmetic unit performs a network process and a specific process that is predetermined to be performed on the message in relation with the network process. An alternate process management table stores therein process... Agent: Turocy & Watson, LLP
20090240927 - Processor and information processing apparatus: A processor capable of executing conditional store instructions without being limited by the number of condition codes is provided. Condition data is stored in floating-point registers, and an operation unit executes a conditional floating-point store instruction of determining whether to store, in cache, store data.... Agent: Staas & Halsey LLP
20090240928 - Change in instruction behavior within code block based on program action external thereto: Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or... Agent: Zagorin O'brien Graham LLP (115)
20090240930 - Executing an application on a parallel computer: Methods, systems, and products are disclosed for executing an application on a parallel computer including a plurality of nodes connected together through a data communications network. Each node has a plurality of processors capable of operating independently for serial processing and capable of operating symmetrically for parallel processing. The application... Agent: Ibm (roc-blf)
20090240929 - Method, system and computer program product for reduced overhead address mode change management in a pipelined, recyling microprocessor: A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090240931 - Indirect function call instructions in a synchronous parallel thread processor: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential... Agent: Patterson & Sheridan, L.L.P.09/17/2009 > patent applications in patent subcategories. class, title,number
20090235047 - Computer system for electronic data processing: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first... Agent: Dicke, Billig & Czaja
20090235048 - Information processing apparatus, signal transmission method, and bridge: Introduced is an end-point bridge that relays an end point—formed by an external bus in a device tree managed by a first processor unit and an end point formed by an external bus in a device tree managed by a second processor unit. A conversion unit in the end-point bridge... Agent: Katten Muchin Rosenman LLP
20090235049 - Method and apparatus for qr-factorizing matrix on a multiprocessor system: The present invention provides a method and apparatus for QR-factorizing matrix on a multiprocessor system, wherein the multiprocessor system comprises at least one core processor and a plurality of accelerators, the method comprises the steps of: iteratively factorizing each panel in the matrix until the whole matrix is factorized; wherein... Agent: Ibm Corporation (swp)
20090235050 - Dynamic service management for multicore processors: A system, apparatus, method and article to perform dynamic service management for multicore processors are described. The apparatus may include, for example, a processing device having multiple types of processors to process packets. A service manager may dynamically assign executable files for multiple services to the multiple types of processors... Agent: Kacvinsky LLC C/o Intellevate
20090235052 - Data processing device and electronic equipment: A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched,... Agent: Hogan & Hartson L.L.P.
20090235051 - System and method of selectively committing a result of an executed instruction: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The... Agent: Qualcomm Incorporated
20090235053 - System and method for register renaming: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090235054 - Disassembling an executable binary: A method for disassembling an executable binary (binary). In one implementation, a plurality of potential address references may be identified based on the binary and a plurality of storage addresses containing the binary. A plurality of assembler source code instructions (instructions) may be generated by disassembling the binary. The binary... Agent: Microsoft Corporation
20090235055 - Scheduling apparatus and scheduling method: A scheduling apparatus includes a state information acquisition unit that acquires, from a decoding unit, state information that serves as an indicator for computing a processing time actually required for a decoding unit to perform a decoding process on first processing target data, and a schedule generating unit that determines... Agent: Katten Muchin Rosenman LLP
20090235057 - Cache memory control circuit and processor: A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having multiple ways; a comparing section configured to detect a cache hit in each way; and a control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090235056 - Recording medium storing performance monitoring program, performance monitoring method, and performance monitoring device: A performance monitoring device has an interrupt detection unit that detects generation of an interrupt process to be executed by a processor in accordance with TLB entry invalidation executed in an operating system. A counter value acquisition unit acquires a counter value of a predetermined event counted by the processor... Agent: Greer, Burns & Crain
20090235058 - Data processing device: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from... Agent: Buchanan, Ingersoll & Rooney PC
20090235059 - Qualification of conditional debug instructions based on address: A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by... Agent: Zagorin O'brien Graham LLP (115)
20090235060 - Data processing apparatus, data processing method and program: A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090235061 - System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.09/10/2009 > patent applications in patent subcategories. class, title,number
20090228681 - Processing unit incorporating instruction-based persistent vector multiplexer control: Persistent vector multiplexer control is used in a vector-based execution unit to control the shuffling of words in operand vectors processed by the execution unit. In addition, a persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090228682 - Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control: A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be stored in... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090228683 - Parallel data processing apparatus: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial... Agent: Glenn Patent Group
20090228684 - Intelligent fabric system on a chip: A chip having an intelligent fabric may include a soft application processor, a reconfigurable hardware intelligent processor, a partitioned memory storage, and an interface to an external reconfigurable communication processor. The reconfigurable hardware intelligent processor may be configured to implement a distributed reconfigurable processor, and to provide cognitive control for... Agent: RozenblatIPLLC And The Boeing Company
20090228685 - System and method for content-based partitioning and mining: Methods and systems are provided for partitioning data of a database or data store into several independent parts as part of a data mining process. The methods and systems use a mining application having content-based partitioning logic to partition the data. Once the data is partitioned, the partitioned data may... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090228686 - Energy efficient processing device: A network processor with a high performance in computing throughput, size and power density for use in applications such as Software Defined Radio (SDR) mesh topology. The network processor uses a core architecture comprised of a programmable microcoded sequencer to implement state management and control, a data manipulation subsystem controlled... Agent: Foley & Lardner LLP
20090228687 - Processor: A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or not a factor obstructing simultaneous execution of the... Agent: Greenblum & Bernstein, P.L.C
20090228688 - Dual function adder for computing a hardware prefetch address and an arithmetic operation value: A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configures for the first... Agent: Qualcomm Incorporated
20090228690 - Early exit processing of iterative refinement algorithm using register dependency disable: An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090228689 - Early exit processing of iterative refinement algorithm using register dependency disable and programmable early exit condition: A programmable “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions.... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090228691 - Arithmetic processing apparatus: An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on... Agent: Greenblum & Bernstein, P.L.C
20090228692 - Load register instruction short circuiting method: An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one... Agent: International Business Machines Corporation Richard Lau
20090228693 - System and method for large microcoded programs: An improved architectural approach for implementation of a microarchitecture for a low power, small footprint microcoded processor for use in packet switched networks in software defined radio MANeTs. A plurality of on-board CPU caches and a system of virtual memory allows the microprocessor to employ a much larger program size,... Agent: Foley & Lardner LLP09/03/2009 > patent applications in patent subcategories. class, title,number
20090222644 - Merge operations of data arrays based on simd instructions: A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge... Agent: Lieberman & Brandsdorfer, LLC
20090222645 - Metric for selective branch target buffer (btb) allocation: A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch... Agent: Freescale Semiconductor, Inc. Law Department
20090222646 - Method and apparatus for detecting processor behavior using instruction trace data: A method and apparatus for detecting processor behavior in real time using instruction trace data, in one aspect, identifies one or more call addresses from which a function to be observed is called and establishes one or more end addresses of the function. Said one or more call addresses and... Agent: Scully, Scott, Murphy & Presser, P.C.
20090222647 - Method and apparatus for reducing test case generation time in processor testing: A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090222648 - Selective postponement of branch target buffer (btb) allocation: A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target... Agent: Freescale Semiconductor, Inc. Law DepartmentPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.