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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) August inventions list 08/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
08/27/2009 > patent applications in patent subcategories. inventions list

20090216996 - Parallel processing: A system and methods comprising a plurality of leaf nodes in communication with one or more branch nodes, each node comprising a processor. Each leaf node is arranged to obtain data indicative of a restriction A|IS of a linear map from Rn to Rm represented by a first matrix, A,... Agent: Patterson, Thuente, Skaar & Christensen, P.a.

20090216997 - Dynamically managing the communication-parallelism trade-off in clustered processors: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected.... Agent: Stolowitz Ford Cowger LLP

20090216998 - Apparatus for and method of processor to processor communication for coprocessor functionality activation: A novel and useful mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The... Agent: Ibm Corporation, T.j. Watson Research Center

20090216999 - Automated execution of virtual appliances: Methods and apparatus, including computer program products, are provided for selecting a processor, such as a hardware provider, for executing a virtual appliance. In one aspect, there is provided a computer-implemented method. The method may include receiving information representative of whether one or more processors are capable of executing at... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.c.

20090217000 - Clock signals in digital systems: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X... Agent: Schmeiser, Olsen & Watts

20090217001 - System and method for handling load and/or store operations in a superscalar microprocessor: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090217003 - Method, system, and computer program product for reducing cache memory pollution: A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217002 - System and method for providing asynchronous dynamic millicode entry prediction: A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217004 - Cache with prefetch: A prefetch bit (126) is associated with cache block (125) of a cache (120), and the management (130) of cache-prefetch operations is based on the state of this bit (126). Further efficiencies are gained by allowing each application to identify memory areas (115) within which regularly repeating memory accesses are... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090217005 - Method, system, and computer program product for selectively accelerating early instruction processing: A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217006 - Heuristic backtracer: A heuristic backtracer is described. In one embodiment, a scanner scans a stack of an application for a pointer to a word of a machine code of the application. A preceding byte locator identifies one or more bytes immediately preceding the pointed-to machine code. A parser parses the one or... Agent: Red Hat/bstz Blakely Sokoloff Taylor & Zafman LLP

20090217007 - Discovery of a virtual topology in a multi-tasking multi-processor environment: A computer program product, apparatus and method for identifying processors in a multi-tasking multiprocessor network, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including storing a service record for a port... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217008 - Program conversion device, and secret keeping program: The program conversion apparatus generates a first instruction group for acquiring values to assign to selection parameters; a second instruction group that includes an instruction group for acquiring, based on an arithmetic expression that uses the selection parameters, a selection identifier showing a selection-target data piece to be processed next;... Agent: Wenderoth, Lind & Ponack L.l.p.

20090217009 - System, method and computer program product for translating storage elements: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217011 - Data processing device and method thereof: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging,... Agent: Larson Newman Abel & Polansky, LLP

20090217010 - Data processor device having trace capabilities and method: In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit... Agent: Larson Newman Abel & Polansky, LLP

20090217012 - Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays: An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217013 - Method and apparatus for programmatically rewinding a register inside a transaction: Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The system then allocates one or more registers for temporary use during the... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090217014 - Processor, memory device, processing device, and method for processing instruction: A processor includes a VM trap logic and a buffering logic. The VM trap logic determines whether or not an instruction acquired from a VM (Virtual Machine) satisfies a predetermined VM trap condition. The buffering logic determines whether or not the instruction acquired from the VM satisfies a predetermined buffering... Agent: Nec Corporation Of America

20090217015 - System and method for controlling restarting of instruction fetching using speculative address computations: A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217016 - System and method for search area confined branch prediction: A system and method for performing search area confined branch prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information for branch prediction, where the branch information includes a branch address. The system also includes search logic for searching the BTB to... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217017 - Method, system and computer program product for minimizing branch prediction latency: A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090217019 - Method for processing interrupt requests in a processor: A method for processing interrupt requests in a processor is suitable for executing at least two threads in parallel, wherein an instruction pipeline is provided for each of the at least two threads. One of the at least two threads is defined as a main thread for processing programs. Another... Agent: Slater & Matsil, L.l.p.

20090217018 - Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory: Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is... Agent: Patterson & Sheridan, LLP/ibm Svl

20090217020 - Commit groups for strand-based computing: Strand-based computing hardware and dynamically optimizing strandware are included in a high performance microprocessor system. The system operates in real time automatically and unobservably to parallelize single-threaded software into parallel strands for execution by cores implemented in a multi-core and/or multi-threaded microprocessor of the system. The system organizes native instructions... Agent: Van Dyke Consulting (st) Client: Strandera

  
08/20/2009 > patent applications in patent subcategories. inventions list

20090210651 - System and method for obtaining data in a pipelined processor: A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210652 - Signal routing in processor arrays: There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the... Agent: Potomac Patent Group PLLC

20090210653 - Method and device for treating and processing data: Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data... Agent: Kenyon & Kenyon LLP

20090210654 - Using historic load profiles to dynamically adjust operating frequency and available power to a handheld multimedia device processor core: A technique is provided for use in a handheld multimedia device that uses the historical load profile statistics of a particular multimedia stream to dynamically scale the computational power of a computing engine, depending upon the complexity of the multimedia content and thereby reduce the power consumption for computationally less... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090210655 - Processor, method and computer program product including specialized store queue and buffer design for silent store implementation: A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210656 - Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor: A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210657 - Multi-microprocessor system and control method for the same: A multi-microprocessor system and a control method for the same are provided. The multi-microprocessor system includes a first microprocessor and a second microprocessor. The second microprocessor is coupled to the first microprocessor. The second microprocessor transmits a detecting signal to the first microprocessor and determines a state of the first... Agent: Wpat, PC

20090210658 - Data processor: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With... Agent: Miles & Stockbridge PC

20090210660 - Prioritising of instruction fetching in microprocessor systems: A method and system are provided for prioritising the fetching of instructions for each of a plurality of executing instruction threads in a multi-threaded processor. Instructions come from at least one source of instructions. Each thread has a number of threads buffered for execution in an instruction buffer 34. A... Agent: Flynn Thiel Boutell & Tanis, P.C.

20090210659 - Processor and method for workaround trigger activated exceptions: A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210661 - Method, system and computer program product for an implicit predicted return from a predicted subroutine: A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210662 - Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system: A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210663 - Power efficient instruction prefetch mechanism: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when... Agent: Qualcomm Incorporated

20090210664 - System and method for issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having four or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210665 - System and method for a group priority issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210667 - System and method for optimization within a group priority issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210666 - System and method for resolving issue conflicts of load instructions: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210675 - Method and system for early instruction text based operand store compare reject avoidance: A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210668 - System and method for optimization within a group priority issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210670 - System and method for prioritizing arithmetic instructions: The present invention provides a system and method for prioritizing arithmetic instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210674 - System and method for prioritizing branch instructions: The present invention provides a system and method for prioritizing branch instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210673 - System and method for prioritizing compare instructions: The present invention provides a system and method for prioritizing compare instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210669 - System and method for prioritizing floating-point instructions: The present invention provides a system and method for prioritizing floating-point instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210671 - System and method for prioritizing store instructions: The present invention provides a system and method for prioritizing store instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210672 - System and method for resolving issue conflicts of load instructions: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210677 - System and method for optimization within a group priority issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210676 - System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline: The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210678 - Handling of denormals in floating point number processim: A data processing apparatus operate to process floating point operands is disclosed. The data processing apparatus comprises: an instruction decoder operable to decode an instruction for processing floating point operands; and a data processor operable to perform data processing operations controlled by the instruction decoder wherein: in response to the... Agent: Nixon & Vanderhye, PC

20090210679 - Processor and method for store data forwarding in a system with no memory model restrictions: A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210681 - Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model: A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can... Agent: International Business Machines Corporation Richard Lau

20090210680 - Method, system and computer program product for millicode store access checking instructions: A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210682 - Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch: Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090210685 - Identification and correction of cyclically recurring errors in one or more branch predictors: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a... Agent: Nixon & Vanderhye, PC

20090210683 - Method and apparatus for recovering from branch misprediction: Embodiments of the present invention provide a system that executes a branch instruction. When executing the branch instruction, the system obtains a stored prediction of a resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction. If an actual resolution... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090210684 - Methods, systems, and computer program products for recovering from branch prediction latency: A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210686 - Method and system for purging pattern history tables as a function of global accuracy in a state machine-based filtered gshare branch predictor: A method, system and computer product for purging pattern history tables as a function of global accuracy in a state machine-based filter gshare branch predictor. An exemplary embodiment includes a method including storing a plurality of encountered branch instructions in the branch history table, indexing the branch history table by... Agent: Cantor Colburn LLP-ibm Poughkeepsie

  
08/13/2009 > patent applications in patent subcategories. inventions list

20090204787 - Butterfly physical chip floorplan to allow an ilp core polymorphism pairing: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204788 - Programmable pipeline array: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell... Agent: Steptoe & Johnson LLP

20090204789 - Distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer: Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application... Agent: Ibm (roc-blf)

20090204790 - Buffer management for real-time streaming: Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that... Agent: Microsoft Corporation

20090204791 - Compound instruction group formation and execution: A method and apparatus for forming compound issue groups containing instructions from multiple cache lines of instructions are provided. By pre-fetching instruction lines containing instructions targeted by a conditional branch statement, if it is predicted that the conditional branch will be taken, a compound issue group may be formed with... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204792 - Scalar processor instruction level parallelism (ilp) coupled pair morph mechanism: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204793 - Raw hazard detection and resolution for implicitly used registers: The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor.... Agent: Prtsi, Inc

20090204794 - Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow: The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204795 - Method and system for automatically testing performance of applications run in a distributed processing structure and corresponding computer program product: Performance of applications run on a distributed processing structure including a grid of processing units is automatically tested by: running at least one application on the distributed processing structure; loading the application with processing workload to thereby produce processing workload on the distributed processing structure; sensing the operating status of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090204796 - Method, system and computer program product for verifying address generation, interlocks and bypasses: Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204797 - Method and system for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching: System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204799 - Method and system for reducing branch prediction latency using a branch target buffer with most recently used column prediction: System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204798 - Simplified implementation of branch target preloading: A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch... Agent: Dillon & Yudell LLP

20090204800 - Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions: The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to... Agent: Huffman Law Group, P.C.

  
08/13/2009 > patent applications in patent subcategories. inventions list

20090204787 - Butterfly physical chip floorplan to allow an ilp core polymorphism pairing: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204788 - Programmable pipeline array: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell... Agent: Steptoe & Johnson LLP

20090204789 - Distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer: Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application... Agent: Ibm (roc-blf)

20090204790 - Buffer management for real-time streaming: Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that... Agent: Microsoft Corporation

20090204791 - Compound instruction group formation and execution: A method and apparatus for forming compound issue groups containing instructions from multiple cache lines of instructions are provided. By pre-fetching instruction lines containing instructions targeted by a conditional branch statement, if it is predicted that the conditional branch will be taken, a compound issue group may be formed with... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204792 - Scalar processor instruction level parallelism (ilp) coupled pair morph mechanism: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090204793 - Raw hazard detection and resolution for implicitly used registers: The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor.... Agent: Prtsi, Inc

20090204794 - Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow: The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204795 - Method and system for automatically testing performance of applications run in a distributed processing structure and corresponding computer program product: Performance of applications run on a distributed processing structure including a grid of processing units is automatically tested by: running at least one application on the distributed processing structure; loading the application with processing workload to thereby produce processing workload on the distributed processing structure; sensing the operating status of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090204796 - Method, system and computer program product for verifying address generation, interlocks and bypasses: Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204797 - Method and system for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching: System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204799 - Method and system for reducing branch prediction latency using a branch target buffer with most recently used column prediction: System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090204798 - Simplified implementation of branch target preloading: A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch... Agent: Dillon & Yudell LLP

20090204800 - Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions: The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to... Agent: Huffman Law Group, P.C.

  
08/06/2009 > patent applications in patent subcategories. inventions list

20090198956 - System and method for data processing using a low-cost two-tier full-graph interconnect architecture: A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198957 - System and method for performing dynamic request routing based on broadcast queue depths: A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198958 - System and method for performing dynamic request routing based on broadcast source request information: A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198959 - Scalable link stack control method with full support for speculative operations: A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090198961 - Cross-thread interrupt controller for a multi-thread processor: An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, the interrupt controller has, for a second thread, an interrupt... Agent: Jay Chesavage

20090198960 - Data processing system, processor and method that support partial cache line reads: According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial read... Agent: Dillon & Yudell LLP

20090198963 - Completion of asynchronous memory move in the presence of a barrier operation: A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation... Agent: Dillon & Yudell LLP

20090198962 - Data processing system, processor and method of data processing having branch target address cache including address type tag bit: In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic... Agent: Dillon & Yudell LLP

20090198965 - Method and system for sourcing differing amounts of prefetch data in response to data prefetch requests: According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to... Agent: Dillon & Yudell LLP

20090198964 - Method, system, and computer program product for out of order instruction address stride prefetch performance verification: A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090198966 - Multi-addressable register file: A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198967 - Method and structure for low latency load-tagged pointer instruction for computer microarchitechture: A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal... Agent: Ibm Microelectronics Intellectual Property Law

20090198968 - Method, apparatus and software for processing software for use in a multithreaded processing environment: A method, apparatus and software for processing software code for use in a multithreaded processing environment in which lock verification mechanisms are automatically inserted in the software code and arranged to determine whether a respective shared storage element is locked prior to the use of the respective shared storage element... Agent: Hamilton & Terrile, LLP IBM Austin

20090198969 - Microprocessor systems: m

20090198971 - Heterogeneous processing elements: A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198970 - Method and structure for asynchronous skip-ahead in synchronous pipelines: An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening... Agent: Mcginn Intellectual Property Law Group, PLLC

20090198972 - Microprocessor systems: If a thread encounters a cache-miss on its passage through the pipeline, the thread is allowed to continue to pass through the pipeline in the normal manner. However, when the thread reaches the end of the pipeline, it is sent via a loopback path 14 back to the beginning of... Agent: Nixon & Vanderhye, PC

20090198973 - Processing circuit: A processing circuit according to the present invention includes a plurality of logic circuits (designated as L11, . . . , and L44) formed by arranging in arrays and is configured to input an output from a logic circuit to the logic circuit located on the following row. Each of... Agent: Mots Law, PLLC

20090198974 - Methods for conflict-free, cooperative execution of computational primitives on multiple execution units: A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or... Agent: Cantor Colburn LLP-ibm Yorktown

20090198976 - Method and structure for high-performance matrix multiplication in the presence of several architectural obstacles: A method (and apparatus) for processing data on a computer having a memory to store the data and a processing unit to execute the processing, the processing unit having a plurality of registers available for an internal working space for a data processing occurring in the processing unit, includes configuring... Agent: Mcginn Intellectual Property Law Group, PLLC

20090198975 - Termination of in-flight asynchronous memory move: A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: (1) an asynchronous memory mover (AMM) store (ST) instruction initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location... Agent: Dillon & Yudell LLP

20090198978 - Data processing apparatus and method for identifying sequences of instructions: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of... Agent: Nixon & Vanderhye, PC

20090198977 - Sharing data in internal and memory representations with dynamic data-driven conversion: Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090198979 - Processor performance state optimization: A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state... Agent: Haynes And Boone, LLPIPSection

20090198980 - Facilitating processing in a computing environment using an extended drain instruction: An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090198981 - Data processing system, processor and method of data processing having branch target address cache storing direct predictions: In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a... Agent: Dillon & Yudell LLP

20090198982 - Data processing system, processor and method of data processing having branch target address cache selectively applying a delayed hit: In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch... Agent: Dillon & Yudell LLP

20090198985 - Data processing system, processor and method of data processing having branch target address cache with hashed indices: In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a... Agent: Dillon & Yudell LLP

20090198984 - Global history branch prediction updating responsive to taken branches: A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process.... Agent: Gerald W. Maliszewski

20090198983 - Global history folding technique optimized for timing: A global history vector (GHV) mechanism maintains a folded GHV with higher order entries an an unfolded GHV with lower order entries. When a new entry arrives at the GHV, the GHV mechanism performs an XOR of the oldest unfolded entry in the unfolded GHV with the new entry. The... Agent: Dillon & Yudell LLP

20090198986 - Configurable instruction sequence generation: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

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