|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
07/2009 | Recent | 14: Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) July category listing 07/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/30/2009 > patent applications in patent subcategories. category listing
20090193225 - System and method for application specific array processing: A processing architecture and methods therein for building application specific array processing utilizing a sequential data bus for control and data propagation. The methods of array processing provided by the architecture allows for numerical analysis of large numerical data such as simulation, image processing, computer modeling or other numerical functions.... Agent: Davis Wright Tremaine, LLP/seattle
20090193226 - Processor for executing highly efficient vliw: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the... Agent: Mcdermott Will & Emery LLP
20090193227 - Multi-stream on-chip memory: An interface to on-chip memory is described, which provides for using on-chip memory by a RISC superscalar processor, enhanced with methods which execute vector operations by treating the vectors as “streams”, which are fed through one or two function units in a pipelined manner. The interface provides concurrent multiple streams,... Agent: Martin Dowd
20090193228 - Multiprocessor system and method of synchronization for multiprocessor system: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of... Agent: Miles & Stockbridge PC
20090193229 - High-integrity computation architecture with multiple supervised resources: The present invention relates to computers, the undetected errors of which have a very low rate of occurrence (approximately 10−9 per time unit). This relates in particular to the embedded computers on aircraft that run critical applications such as the automatic pilot, flight management, fuel management or terrain collision prevention.... Agent: Darby & Darby P.C.
20090193230 - Computer system including a main processor and a bound security coprocessor: A computer system includes a main processor and a security control processor that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090193232 - Apparatus, processor and method of cache coherency control: An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends... Agent: Mcginn Intellectual Property Law Group, PLLC
20090193231 - Method and apparatus for thread priority control in a multi-threaded processor of an information handling system: An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a... Agent: Mark P. Kahler
20090193233 - Mechanism for avoiding check stops in speculative accesses while operating in real mode: A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the... Agent: Ibm Corporation Intellectual Property Law
20090193234 - Sequencer controlled system and method for controlling timing of operations of functional units: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer... Agent: Birch Stewart Kolasch & Birch
20090193236 - Conditional memory ordering: A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where... Agent: Michael Buchenhorner, P.A.
20090193235 - Transfer system, and transfer method: In response to a transfer request, for which a loading time at a transfer source and a loading time at a transfer target are designated by a production controller, there is created a transfer scenario, which contains a basic transfer (From) from the transfer source to a buffer near the... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090193237 - Parsing-enhancement facility: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20090193238 - Reconfigurable apparatus and method for providing multiple modes: A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing... Agent: Mcneely Bodendorf LLP
20090193239 - Counter control circuit, dynamic reconfigurable circuit, and loop processing control method: A counter control circuit that controls the operation of a counter arranged in a dynamic reconfigurable circuit executing an arbitrary instruction by dynamically switching an aggregation of reconfigurable processing elements (hereinafter referred to as “PEs”) according to a context reciting a processing content of the PE and a connection content... Agent: Arent Fox LLP
20090193240 - Method and apparatus for increasing thread priority in response to flush information in a multi-threaded processor of an information handling system: An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread... Agent: Mark P. Kahler
20090193241 - Direct register access for host simulation: Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Various implementations of the invention provide for... Agent: Mentor Graphics Corp. Patent Group07/23/2009 > patent applications in patent subcategories. category listing
20090187733 - Virtual configuration management for effiicient use of reconfigurable hardwware: Simulations, as well as emulation using the Cray XD1 reconfigurable high-performance computer were used for the experimental study. The results show a significant improvement in performance using the proposed techniques. This improvement can be assessed by computing the speedup. This speedup shows that the proposed segmentation technique is almost twice... Agent: Juneau Partners
20090187734 - Efficient texture processing of pixel groups with simd execution unit: A circuit arrangement and method perform concurrent texture processing of groups of pixels with a single instruction multiple data (SIMD) execution unit to improve the utilization of the SIMD execution unit when performing scalar operations associated with a texture processing algorithm. In addition, when utilized in connection with a multi-threaded... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090187735 - Microcontroller having dual-core architecture: A microcontroller having dual-core architecture is provided. Using a unique hardware configuration of memories, control registers and reset machines, the invention not only reduces hardware cost, but also improves management efficiency and system stability.... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090187736 - Computing device, a system and a method for parallel processing of data streams: A computing arrangement for identification of a current temporal input against one or more learned signals. The arrangement comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core... Agent: Myers Wolin, LLC
20090187737 - Image forming apparatus: A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access registers arranged in stages for storing image data; and multiple data processing devices corresponding one-to-one with the stages of the access registers, arranged... Agent: Cooper & Dunham, LLP
20090187738 - Simd-type microprocessor, method of processing data, image data processing system, and method of processing image data: Disclosed is an SIMD-type microprocessor comprising a processor element group, plural processor elements with an operation part and a register file being arranged therein and a processor element control signal generator configured to output a processor element control signal controlling an operation of the processor element, wherein a feed part... Agent: Cooper & Dunham, LLP
20090187739 - Method and apparatus for improved computer load and store operations: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090187740 - Reducing errors in pre-decode caches: In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded,... Agent: Nixon & Vanderhye, PC
20090187741 - Data processing apparatus and method for handling instructions to be executed by processing circuitry: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation... Agent: Nixon & Vanderhye, PC
20090187743 - Data processing apparatus and method for instruction pre-decoding: The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing... Agent: Nixon & Vanderhye, PC
20090187744 - Data processing apparatus and method for pre-decoding instructions: A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in a cache for access by processing circuitry. For a first... Agent: Nixon & Vanderhye, PC
20090187742 - Instruction pre-decoding of multiple instruction sets: A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding... Agent: Nixon & Vanderhye, PC
20090187745 - Information processing system and method of executing firmware: An information processing system includes a control central processing unit a memory; and a stream interface configured to receive an input stream including data to be processed and to transfer the input stream to the memory. A download process in which the stream interface receives stream data including firmware and... Agent: Fujitsu Patent Center C/o Cpa Global
20090187746 - Apparatus and method for performing permutation operations on data: An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged... Agent: Nixon & Vanderhye P.C.
20090187748 - Method and system for detecting stack alteration: The disclosed systems and methods relate to employing one or more of machine instructions (i.e. assembler language instructions) to detect stack alterations. Aspects of the present invention also relate to employing CPU logic and one or more associated CPU registers to detect stack alterations. Aspects of the present invention may... Agent: Mcandrews Held & Malloy, Ltd
20090187747 - System and method for tracing instruction pointers and data access: A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit configured to perform an instruction pointer trace, and at least one second trace unit configured to perform a data... Agent: Dicke, Billig & Czaja
20090187749 - Pipeline processor: A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090187750 - Binary translator with precise exception synchronization mechanism: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides... Agent: Vmware, Inc.07/16/2009 > patent applications in patent subcategories. category listing
20090182978 - Real-time cpu dispatcher affinity re-balancing: A method and apparatus of operating a central processing unit (CPU) including a plurality of processors, is provided and includes collecting real-time statistics relating to the processors during dispatching activities, identifying give-help processors from the real-time statistics when the real-time statistics indicate that one or more of the nodes is... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090182979 - Computer configuration virtual topology discovery and instruction therefore: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology... Agent: International Business Machines Corporation Richard Lau
20090182980 - Systems and methods for asymmetric multiprocessing: Systems and methods are described for managing applications in a computer system. An operating system kernel such as Linux can be started and executed at different addresses other than the address typically used for such kernels. An operating system kernel can accommodate end of memory and size of memory that... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090182982 - Rotate then insert selected bits facility and instructions therefore: A rotate then operate instruction having a Z bit is fetched and executed wherein a first operand in a first register is rotated by an amount. If the Z bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second... Agent: International Business Machines Corporation Richard Lau
20090182981 - Rotate then operate on selected bits facility and instructions therefore: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register.... Agent: International Business Machines Corporation Richard Lau
20090182983 - Compare and branch facility and instruction therefore: An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained... Agent: International Business Machines Corporation Richard Lau
20090182984 - Execute relative long facility and instructions therefore: A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter... Agent: International Business Machines Corporation Richard Lau
20090182985 - Move facility and instructions therefore: A move instruction, having a signed immediate field, copies a sign extended signed immediate field value to an operand location in memory. The size of the operand is determined by the opcode of the instruction. Preferably, the address of the operand is determined by adding a displacement field of the... Agent: International Business Machines Corporation Richard Lau
20090182986 - Processing unit incorporating issue rate-based predictive thermal management: A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are issued to one or more execution units in the processing unit, and selectively delays the issuance of subsequent instructions to the execution... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090182987 - Processing unit incorporating multirate execution unit: A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the execution unit can be clocked at a rate... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090182988 - Compare relative long facility and instructions therefore: A method, system and program product for comparing two operands wherein one operand is obtained from memory wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction... Agent: International Business Machines Corporation Richard Lau
20090182989 - Multithreaded microprocessor with register allocation based on number of active threads: A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.... Agent: Fish & Richardson, PC
20090182990 - Method and apparatus for a pipelined multiple operand minimum and maximum function: Embodiments of the invention provide methods and apparatus for executing a multiple operand minimum or maximum instructions. Executing the multiple operand minimum or maximum instruction comprises transferring more than two operands to one or more processing lanes of a vector unit. A first compare operation may be performed in at... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090182991 - Processor including efficient signature generation for logic error protection: A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090182993 - Concurrent processing element system, and method: An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and,... Agent: Steptoe & Johnson LLP
20090182992 - Load relative and store relative facility and instructions therefore: A method, system and program product for loading or storing memory data wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and... Agent: International Business Machines Corporation Richard Lau
20090182994 - Two-level representative workload phase detection method, apparatus, and computer usable program code: A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at... Agent: Ibm Corp (ya) C/o Yee & Associates PC07/09/2009 > patent applications in patent subcategories. category listing
20090177862 - Input device for executing an instruction code and method and interface for generating the instruction code: An input device for executing an instruction code and method and interface for generating the instruction code are disclosed. The method for generating an instruction code which is executed by an input device includes the steps of: opening a specific purpose programming interface which is used for simulating to show... Agent: Rosenberg, Klein & Lee
20090177863 - Hierarchical management of realtime edge processor: A hierarchical network infrastructure includes an interface that allows a user to define a management hierarchy between a plurality of edge processors. Input is received via the interface designating a management node and a first set of relationships between the management mode and at least one edge processor. A management... Agent: Townsend And Townsend And Crew LLP
20090177864 - Multiprocessor computing systems with heterogeneous processors: Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical results upon executing any command in the baseline command set. The processors also... Agent: Townsend And Townsend And Crew LLP
20090177865 - Extensible microcomputer architecture: Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path... Agent: Microsoft Corporation
20090177866 - System and method for functionally redundant computing system having a configurable delay between logically synchronized processors: A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to a functional unit in the computer system. A system response from the functional unit is then... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090177867 - Processor architectures for enhanced computational capability: A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at... Agent: Wolf Greenfield & Sacks, P.C.
20090177868 - Apparatus, system, and method for discontiguous multiple issue of instructions: An apparatus, system, and method are disclosed for discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The plurality of issue units each comprises a renaming map that maps each architecturally visible register address to a rename register. Each... Agent: Kunzler & Mckenzie
20090177869 - Efficient check node message transform approximation for ldpc decoder: In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp... Agent: Qualcomm Incorporated
20090177870 - Method and system for a wiring-efficient permute unit: A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical... Agent: Dillon & Yudell LLP
20090177871 - Architectural support for software thread-level speculation: A system for thread-level speculation includes a memory system for storing a program code, a plurality of registers corresponding to one or more execution contexts, for storing sets of memory addresses that are accessed speculatively, and a plurality of processors, each providing the one or more execution contexts, in communication... Agent: F. Chau & Associates, LLC
20090177872 - Method and system for generating a valid signal: A method for generating a valid signal for an application program in a signal processing system having a plurality of execution units which operate in a performance mode, and in which while the application program is running, a user switches the signal processing system to a comparison mode in which... Agent: Kenyon & Kenyon LLP
20090177873 - Instruction generation apparatus: A tampering-prevention-process generation apparatus (110) which generates a program that reliably protects a code targeted for protection is an apparatus that generates an output process instruction group (160) to be executed by an execution processing apparatus (130) in order to protect a first process instruction (140) which causes the execution... Agent: Wenderoth, Lind & Ponack L.L.P.
20090177874 - Processor apparatus and conditional branch processing method: Disclosed is a processor apparatus including a branch condition storage unit having a plurality of storage regions in each of which a branch condition set by a condition setting instruction is stored, an instruction decoder that decodes an instruction code, an instruction memory that stores therein the instruction code, an... Agent: Mcginn Intellectual Property Law Group, PLLC
20090177875 - Branch target buffer addressing in a data processor: A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch... Agent: Freescale Semiconductor, Inc. Law Department07/02/2009 > patent applications in patent subcategories. category listing
20090172349 - Methods, apparatus, and instructions for converting vector data: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a... Agent: Intel Corporation C/o Cpa Global
20090172348 - Methods, apparatus, and instructions for processing vector data: A computer processor includes control logic for executing LoadUnpack and PackStore instructions. In one embodiment, the processor includes a vector register and a mask register. In response to a PackStore instruction with an argument specifying a memory location, a circuit in the processor copies unmasked vector elements from the vector... Agent: Intel Corporation C/o Cpa Global
20090172350 - Non-volatile processor register: A processor using a vertically configured non-volatile memory array that can retain values through a power failure is disclosed. The processor may include a register block configured to store and retrieve one or more values, the register block being a vertically configured non-volatile memory array, an arithmetic block configured to... Agent: Unity Semiconductor Corporation
20090172351 - Data processing device and method: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher... Agent: Kenyon & Kenyon LLP
20090172352 - Dynamic reconfigurable circuit: A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network that is coupled to the arithmetic data input ports and the output ports of the plurality of processing elements, a... Agent: Staas & Halsey LLP
20090172353 - System and method for architecture-adaptable automatic parallelization of computing code: Systems and methods for architecture-adaptable automatic parallelization of computing code are described herein. In one aspect, embodiments of the present disclosure include a method of generating a plurality of instruction sets from a sequential program for parallel execution in a multi-processor environment, which may be implemented on a system, of,... Agent: Perkins Coie LLP
20090172354 - Handshaking dual-processor architecture of digital camera: A handshaking dual-processor architecture of a digital camera includes a microprocessor and a digital signal processor (DSP). After accepting a user command, the microprocessor transmits a wakeup signal to trigger the DSP to switch from a sleep mode to an operation mode, and transmits a data packet and a processing... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090172355 - Instructions with floating point control override: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described.... Agent: Caven & Aghevli LLC C/o Cpa Global
20090172356 - Compressed instruction format: A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090172358 - In-lane vector shuffle instructions: In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions... Agent: Larry Mennemeier Intel Corporation
20090172357 - Using a processor identification instruction to provide multi-level processor topology information: Embodiments of an invention for using a processor identification instruction to provide multi-level processor topology information are disclosed. In one embodiment, a processor includes decode logic and control logic. The decode logic is to receive an identification instruction having an associated topological level value. The control logic is to provide,... Agent: Intel Corporation C/o Cpa Global
20090172359 - Processing pipeline having parallel dispatch and method thereof: One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor... Agent: Larson Newman Abel & Polansky, LLP
20090172360 - Information processing apparatus equipped with branch prediction miss recovery mechanism: The information processing apparatus comprises a cache miss detection unit detects a cache miss of a load instruction; an instruction issuance stop unit stops the issuance of an instruction subsequent to a conditional branch instruction if the branch direction of a conditional branch instruction subsequent to the load instruction for... Agent: Staas & Halsey LLP
20090172361 - Completion continue on thread switch mechanism for a microprocessor: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a... Agent: Larson Newman Abel & Polansky, LLP
20090172362 - Processing pipeline having stage-specific thread selection and method thereof: One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor... Agent: Larson Newman Abel & Polansky, LLP
20090172364 - Device, system, and method for gathering elements from memory: A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the... Agent: Pearl Cohen Zedek Latzer, LLP
20090172366 - Enabling permute operations with flexible zero control: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values. Multiple permute instructions may be combined to perform efficient table lookups.... Agent: Trop, Pruner & Hu, P.C.
20090172365 - Instructions and logic to perform mask load and store operations: In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed.... Agent: Trop, Pruner & Hu, P.C.
20090172363 - Mixing instructions with different register sizes: When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they... Agent: Intel Corporation C/o Cpa Global
20090172367 - Processing unit: A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into... Agent: Staas & Halsey LLP
20090172368 - Hardware based runtime error detection: A processor that includes a storage medium which includes microcode that performs runtime analysis. The storage medium can include instrumented microcode that monitors at least one execution of a machine instruction resulting in a memory access, instrumented microcode that accesses at least one memory state indicator to determine whether the... Agent: Cuenot, Forsythe & Kim
20090172369 - Saving and restoring architectural state for processor cores: A method and apparatus for saving and restoring architectural states utilizing hardware is herein described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to... Agent: Intel Corporation C/o Cpa Global
20090172370 - Eager execution in a processing pipeline having multiple integer execution units: One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor... Agent: Larson Newman Abel & Polansky, LLP
20090172371 - Feedback mechanism for dynamic predication of indirect jumps: Systems and methods are provided to detect instances where dynamic predication of indirect jumps (DIP) is considered to be ineffective utilizing data collected on the recent effectiveness of dynamic predication on recently executed indirect jump instructions. Illustratively, a computing environment comprises a DIP monitoring engine cooperating with a DIP monitoring... Agent: Turocy & Watson, LLP
20090172372 - Methods and apparatus for generating system management interrupts: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each... Agent: Barnes & Thornburg, LLPPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20140410:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.59946 seconds