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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) June invention type 06/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
06/25/2009 > patent applications in patent subcategories. invention type

20090164751 - Method,system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning: Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a socket, that may utilize a different operating system, access to the shared resource based at least in part on whether an assigned... Agent: Trop, Pruner & Hu, P.C.

20090164752 - Processor memory system: A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly... Agent: Potomac Patent Group PLLC

20090164753 - Operation, control, branch vliw processor: An Operation, Compare, Branch (OCB) VLIW instruction word has a memory address, a respective operation code, a respective comparison and branch code; and at least two respective branch pointers. A plurality of OCB VLIW instructions are contained in memory. The branch pointers of a given instruction word connect to a... Agent: Department Of The Army Legal Office

20090164754 - Hierarchical block-identified data communication for unified handling of structured data and data compression: Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted... Agent: Lumen Patent Firm

20090164755 - Optimizing execution of single-threaded programs on a multiprocessor managed by compilation: A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an... Agent: Hamilton & Terrile, LLP IBM Austin

20090164756 - Geological response data imaging with stream processors: The invention describes a method to convert geological response data to graphical raw data by using at least one stream processor for this purpose. The geological response data is pre-processed by a CPU and the preprocessed geological response data is fed into one or more stream processors. The stream processor... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090164757 - Method and apparatus for performing out of order instruction folding and retirement: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for increasing a number of instructions per clock cycle associated with a processor. The illustrative embodiments fold a plurality of non-sequential instructions within the set of sequential order instructions to form a folded instruction. The... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090164758 - System and method for performing locked operations: A mechanism for performing locked operations in a processing unit. A dispatch unit may dispatch a plurality of instructions including a locked instruction and a plurality of non-locked instructions. One or more of the non-locked instructions may be dispatched before and after the locked instruction. An execution unit may execute... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090164759 - Execution of single-threaded programs on a multiprocessor managed by an operating system: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to... Agent: Hamilton & Terrile, LLP IBM Austin

20090164760 - Method and system for module initialization with an arbitrary number of phases: A method for initializing a module that includes identifying a first module for initialization, and performing a plurality of processing phases on the first module and all modules in a dependency graph of the first module. Performing the plurality of processing phases includes, for each module, executing a processing phase... Agent: Osha Liang L.L.P./sun

20090164761 - Hierarchical system and method for analyzing data streams: A method for analyzing data streams comprises receiving a data stream, conducting a first analysis of the data stream for a possible target activity, and if a possible target activity is indicated generating a first alert. If the first alert is generated, a second analysis for the possible target activity... Agent: Knobbe Martens Olson & Bear LLP

20090164762 - Optimizing xor-based codes: A “code optimizer” provides various techniques for optimizing arbitrary XOR-based codes for encoding and/or decoding of data. Further, the optimization techniques enabled by the code optimizer do not depend on any underlining code structure. Therefore, the optimization techniques provided by the code optimizer are applicable to arbitrary codes with arbitrary... Agent: Microsoft Corporation C/o Lyon & Harr, LLP

20090164763 - Method and apparatus for a double width load using a single width load port: A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.... Agent: Intel Corporation C/o Cpa Global

20090164764 - Processor and debugging device: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction... Agent: Mcdermott Will & Emery LLP

20090164765 - Determining thermal characteristics of instruction sets: Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each... Agent: International Corp (blf)

20090164766 - Branch history with polymorphic indirect branch information: A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

06/18/2009 > patent applications in patent subcategories. invention type

20090158007 - Scaleable array of micro-engines for waveform processing: A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent... Agent: Ratnerprestia

20090158008 - Software parameterizable control blocks for use in physical layer processing: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing... Agent: Volpe And Koenig, P.C. Dept. Icc

20090158009 - Electronic equipment and control method: Plural CPUs are provided, and when a first CPU of the plural CPUs is a master, the other CPU operates as a slave. Also, plural memories are provided including a memory that operates and is used for first processing when the master CPU operates and a memory that operates and... Agent: Amin, Turocy & Calvin, LLP

20090158010 - Command protocol for integrated circuits: A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be... Agent: Edell, Shapiro & Finnan, LLC

20090158011 - Data processing system: A data processing system comprising a computer chip having a processing circuit and a chip-internal first memory and a chip-external second memory being coupled to the computer chip, wherein the processing circuit is configured to allow execution of computer programs stored in the first memory and to prevent execution of... Agent: Dickstein Shapiro LLP

20090158012 - Method and apparatus for performing improved group instructions: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20090158013 - Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor: Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090158014 - System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor: An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090158015 - Uses of known good code for implementing processor architectural modifications: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090158016 - Use of modes for computer cluster management: A system, method and computer program product for managing a plurality of applications in a computer cluster. Each application is able to run on a particular node in the cluster. In one embodiment, associations are maintained among a plurality of modes and the plurality of applications, with each application being... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090158017 - Target-frequency based indirect jump prediction for high-performance processors: A frequency-based prediction of indirect jumps executing in a computing environment is provided. Illustratively, a computing environment comprises a prediction engine that processes data representative of indirect jumps performed by the exemplary computing environment according to a selected frequency-based prediction paradigm. Operatively, the exemplary prediction engine can keep track of... Agent: Amin, Turocy & Calvin, LLP

20090158018 - Method and system for auto parallelization of zero-trip loops through the induction variable substitution: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090158019 - Computer program code size partitioning system for multiple memory multi-processing systems: The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

06/11/2009 > patent applications in patent subcategories. invention type

20090150647 - Processing unit incorporating vectorizable execution unit: A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical execution units in different modes. By doing so, processing lanes can be selectively grouped together to operate as different types of... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090150649 - Capacity register file: An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in... Agent: CenturyIPGroup, Inc. [intel]

20090150648 - Vector permute and vector register file write mask instruction variant state extension for risc length vector instructions: Embodiments of the invention generally relate to the field of image processing, and more specifically to instructions and hardware for supporting image processing. An integrated processing unit configured to process vector instructions and vector permute instructions is provided. A vector permute instruction may be issued to the integrated processing unit... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090150650 - Kernel processor grouping: Techniques for grouping individual processors into assignment entities are discussed. Statically grouping processors may permit threads to be assigned on a group basis. In this manner, the burden of scheduling threads for processing may be minimized, while the processor within the assignment entity may be selected based on the physical... Agent: Lee & Hayes, PLLC

20090150651 - Semiconductor chip: Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on... Agent: Rader Fishman & Grauer PLLC

20090150652 - Computer monitoring system and monitoring method: An exemplary computer monitoring system includes a central processing unit (CPU) connected to a computer, a first microprocessor, a second microprocessor, and a select switch connected to a terminal device. The CPU is connected to the select switch via the first microprocessor and the second microprocessor respectively for transmitting data.... Agent: PCe Industry, Inc. Att. Steven Reiss

20090150653 - Mechanism for soft error detection and recovery in issue queues: In one embodiment, the present invention includes logic to detect a soft error occurring in certain stages of a core and recover from such error if detected. One embodiment may include logic to determine if a lapsed time from a last instruction to issue from an issue stage of a... Agent: Trop, Pruner & Hu, P.C.

20090150654 - Fused multiply-add functional unit: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that... Agent: Townsend And Townsend And Crew LLP

20090150655 - Method of updating register, and register and computer system to which the method can be applied: A register updating method includes generating third information including first information and second information, wherein the first information indicates whether updating of regions of a register block is allowed and the second information includes information that is to be updated in the register block, transmitting the third information to an... Agent: F. Chau & Associates, LLC

20090150656 - Reducing aging effect on registers: Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.... Agent: Caven & Aghevli LLC C/o Cpa Global

20090150657 - Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system: An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the... Agent: Mark P. Kahler

20090150658 - Processor and signal processing method: This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch instruction to the instruction execution unit. The... Agent: Texas Instruments Incorporated

06/04/2009 > patent applications in patent subcategories. invention type

20090144521 - Method and apparatus for searching extensible markup language (xml) data: Extensible Markup Language (XML) data is represented as a list of structures with each structure in the list representing an aspect of the XML. A set of frequently used elements is extracted from the list of structure representation and stored in packed vectors. The packed vector representation allows Single Instruction... Agent: Caroline F. Fleming Intel Corporation

20090144522 - Data processing device and method: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher... Agent: Kenyon & Kenyon LLP

20090144523 - Multiple-simd processor for processing multimedia data and arithmetic method using the same: A multiple-single instruction multiple data (SIMD) processor and an arithmetic method using the same are disclosed. When various arithmetic operations should be individually carried out by SIMD arithmetic units, control right is sub-divided to perform the arithmetic operations, such that the time of the arithmetic operations can be shortened and... Agent: Ladas & Parry LLP

20090144524 - Method and system for handling transaction buffer overflow in a multiprocessor system: There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and... Agent: Ibm Corporation (swp)

20090144525 - Apparatus and method for scheduling threads in multi-threading processors: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of... Agent: Kenyon & Kenyon LLP

20090144526 - System and method of accessing a device: A method of accessing a device is provided. A command is received from an agent, over a network, for executing at least one instruction for accessing the device. Information is sent to the agent, over the network, regarding the execution of the at least one instruction.... Agent: Dicke, Billig & Czaja

20090144527 - Stream processing apparatus, method for stream processing and data processing system: The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control... Agent: Mattingly & Malur, P.C.

20090144528 - Method for running native code across single or multi-core hybrid processor achitecture: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is... Agent: Greg Goshorn, P.C.

20090144529 - Simd code generation for loops with mixed data lengths: Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

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