|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
05/2009 | Recent | 15: Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) May archived by USPTO category 05/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/28/2009 > patent applications in patent subcategories. archived by USPTO category
20090138674 - Electronic system for changing number of pipeline stages of a pipeline: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control... Agent: North America Intellectual Property Corporation
20090138675 - Atomic compare and swap using dedicated processor: An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on an address in main memory. The address has a size... Agent: Joshua D. Isenberg Jdi Patent
20090138676 - Design structures including circuits for noise reduction in digital systems: A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of... Agent: Schmeiser, Olsen & Watts
20090138677 - System for native code execution: A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native... Agent: Henneman & Associates, PLC
20090138679 - Enhanced boolean processor: A processor including a Boolean logic unit, wherein the Boolean logic unit is operated for performing the short-circuit evaluation of a Normal Form Boolean expression/operation, a plurality of input/output interfaces in communication with the Boolean logic unit, wherein the plurality of input/output interfaces are operated for receiving a plurality of... Agent: Kilpatrick Stockton LLP - 46872 J. Steven Gardner
20090138678 - Multifunction hexadecimal instruction form system and program product: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point... Agent: International Business Machines Corporation
20090138680 - Vector atomic memory operations: A processor is operable to execute one or more vector atomic memory operations. A further embodiment provides support for atomic memory operations in a memory manger, which is operable to process atomic memory operations and to return a completion notification or a result.... Agent: Schwegman, Lundberg & Woessner, P.A.
20090138681 - Synchronization of parallel processes: A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution... Agent: Fish & Richardson, PC
20090138682 - Dynamic instruction execution based on transaction priority tagging: A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for... Agent: Hamilton & Terrile, LLP IBM Austin
20090138683 - Dynamic instruction execution using distributed transaction priority registers: A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values in... Agent: Hamilton & Terrile, LLP IBM Austin
20090138684 - H.264 cavlc decoding method based on application-specific instruction-set processor: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in... Agent: Rabin & Berdo, PC
20090138686 - Method for processing a graph containing a set of nodes: The invention relates to a computerized method for processing a graph containing a set of nodes processing a graph containing a set of nodes, wherein forest of trees is provided corresponding to a directed acyclic graph containing a set of nodes, each of said nodes having a type chosen from... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg
20090138685 - Processor for processing instruction set of plurality of instructions packed into single code: A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in... Agent: Buchanan, Ingersoll & Rooney PC
20090138687 - Memory device having data processing function: A memory device having a data processing function is disclosed. The memory device can include a process area, in which process command information is written by a processor; a storage area, in which one or more data is written; an output area, in which display data selected by the processor... Agent: Birch Stewart Kolasch & Birch
20090138688 - Multi-die processor: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090138689 - Partitioning processor resources based on memory usage: Processor resources are partitioned based on memory usage. A compiler determines the extent to which a process is memory-bound and accordingly divides the process into a number of threads. When a first thread encounters a prolonged instruction, the compiler inserts a conditional branch to a second thread. When the second... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090138690 - Local and global branch prediction information storage: Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch prediction information, a second table for storing global branch prediction information, and circuitry. The circuitry is configured to receive a branch instruction and... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-105/21/2009 > patent applications in patent subcategories. archived by USPTO category
20090132786 - Method and system for local memory addressing in single instruction, multiple data computer system: A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local... Agent: Karen Henckel, Esq. Dorsey & Whitney LLP
20090132785 - Simd processor executing min/max instructions: A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output... Agent: Mcandrews Held & Malloy, Ltd
20090132787 - Runtime instruction decoding modification in a multi-processing array: A method and system for decoding and modifying processor instructions in runtime according to certain rules in order to separately control processing elements embedded within a multi-processor array using a single instruction. The present invention allows multiple processing elements and/or execution units in a multi-processor array to perform different operations,... Agent: Stevens Law Group
20090132788 - Control system with multiple processors and control method thereof: A control system comprises a master processor, a main memory and multiple slave processors. The main memory stores programs, and a signal-program table for storing relationships between the programs and input signals. The multiple slave processors are configured for sending input signals in response to external stimuli to the master... Agent: PCe Industry, Inc. Att. Steven Reiss
20090132789 - Apparatus and method for channel-specific configuration in a readout asic: An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality... Agent: General Electric Company Global Research
20090132790 - System and method for processor with predictive memory retrieval assist: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090132791 - System and method for recovering from a hang condition in a data processing system: A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache... Agent: Dillon & Yudell LLP
20090132792 - Method of generating internode timing diagrams for a multiprocessor array: The apparatus used includes a multi core computer processor 10 where a plurality of processors 15 is located on a single substrate 25. Processors 15 are connected to their nearest neighbor directly by single drop data busses 20. The method is executed by an application code that includes functions which... Agent: Henneman & Associates, PLC
20090132794 - Method and apparatus for performing complex calculations in a multiprocessor array: A method and apparatus for performing complex mathematical calculations. The apparatus includes a multicore processor 10 where the cores 15 are connected 20 into a net with the processors on the periphery 15a primarily dedicated to input/output functions and distribution of tasks to the central processors 15b-h of the net.... Agent: Henneman & Associates, PLC
20090132793 - System and method of selectively accessing a register file: In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The... Agent: Qualcomm Incorporated
20090132795 - Processor with excludable instructions and registers and changeable instruction coding for antivirus protection: Digital processor architecture is characterized by processor's instruction set and registers. If architecture is fixed and known to software developers the viruses may be created to harm computers. Invented processor architecture protects against viruses by modifying of association between instruction set coding and processor's functions. Additionally, invented architecture allows to... Agent: Mikhail Y. Vlasov
20090132796 - Polling using reservation mechanism: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can... Agent: Larson Newman Abel & Polansky, LLP05/14/2009 > patent applications in patent subcategories. archived by USPTO category
20090125702 - Simd processor and addressing method: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register.... Agent: Mcandrews Held & Malloy, Ltd
20090125703 - Context switching on a network on chip: Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, with each IP block also adapted to the network by... Agent: Ibm (roc-blf)
20090125704 - Design structure for dynamically selecting compiled instructions: A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution... Agent: Cantor Colburn LLP-ibm Burlington
20090125705 - Data processing method and apparatus with respect to scalability of parallel computer systems: A data processing method for scalability of a parallel computer system includes: obtaining a processing time τ(p) that is the longest processing time in a case where a parallel processing is carried out by p processors and a processing time γi(p) (i represents a processor number) that is a processing... Agent: Staas & Halsey LLP
20090125706 - Software pipelining on a network on chip: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory,... Agent: Ibm (roc-blf)
20090125707 - System and method for speculative global history prediction updating: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch... Agent: Gerald W. Maliszewski05/07/2009 > patent applications in patent subcategories. archived by USPTO category
20090119479 - Integrated circuit arrangement for carrying out block and line based processing of image data: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24)... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090119480 - Method, system and program for developing and scheduling adaptive integrated circuitry and corresponding control or configuration information: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of... Agent: Nixon Peabody LLP
20090119481 - Computer memory architecture for hybrid serial and parallel computing systems: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions... Agent: Gamburd Law Group LLC
20090119482 - Image forming device, image formation controlling method, and image formation controlling program: An image forming device includes a plurality of input units, a plurality of processing units, and a plurality of output units which are arranged to perform image-data processing. The image forming device includes a processing operation executing unit configured to instruct a processing operation of each of a predetermined input... Agent: Harness, Dickey & Pierce, P.L.C
20090119483 - Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens: Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.
20090119484 - Method and apparatus for implementing digital logic circuitry: A method of generating digital control parameters for implementing digital logic circuitry comprising functional nodes with at least one input or at least one output and connections indicating interconnections between said functional nodes, wherein said digital logic circuitry comprises a first path streamed by successive tokens, and a second path... Agent: Harness, Dickey & Pierce, P.L.C
20090119487 - Arithmetic processing apparatus for executing instruction code fetched from instruction cache memory: An arithmetic processing apparatus includes a cache block which stores a plurality of instruction codes from a main memory, a central processing unit which fetch-accesses the cache block and sequentially loads and executes the plurality of instruction codes, and a repeat buffer which stores an instruction code group corresponding to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090119486 - Method and a system for accelerating procedure return sequences: A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the... Agent: Qualcomm Incorporated
20090119485 - Predecode repair cache for instructions that cross an instruction cache line: A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length... Agent: Qualcomm Incorporated
20090119488 - Prefetch unit: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090119489 - Methods and apparatus for transforming, loading, and executing super-set instructions: Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a... Agent: Peter H. Priest
20090119490 - Processor and instruction scheduling method: An instruction scheduling method and a processor using an instruction scheduling method are provided. The instruction scheduling method includes selecting a first instruction that has a highest priority from a plurality of instructions, and allocating the selected first instruction and a first time slot to one of the functional units,... Agent: Mcneely Bodendorf LLP
20090119491 - Data processing device: A data processing device comprises a state manager for determining a logic number of configurational information to be used in a next state, the logic number representing information on a mutual relationship between items of configurational information included in an object code, based on a present operational state, a group... Agent: Scully Scott Murphy & Presser, PC
20090119492 - Data processing apparatus and method for handling procedure call instructions: A data processing apparatus and method are provided for handling procedure call instructions. The data processing apparatus has processing logic for performing data processing operations specified by program instructions fetched from a sequence of addresses, at least one of the program instructions being a procedure call instruction specifying a branch... Agent: Nixon & Vanderhye P.C.
20090119493 - Using branch instruction counts to facilitate replay of virtual machine instruction execution: A method and computer program product for logging non-deterministic events of a virtual machine executing a sequence guest instructions, the method including tracking an execution point in the sequence of executing guest instructions, the tracking of the execution point including determining a branch count of executed branch instructions; and detecting... Agent: Vmware, Inc.
20090119494 - Design structure for predictive decoding: A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior instruction execution characteristics; logic for obtaining predictor information for the fetched instruction from the... Agent: Cantor Colburn LLP-ibm Burlington
20090119495 - Architectural enhancements to cpu microde load mechanism for information handling systems: A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other... Agent: Hamilton & Terrile, LLPPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150423:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.4501 seconds