|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
04/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) April category listing, related patent applications 04/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/30/2009 > patent applications in patent subcategories.
20090113168 - Software pipelining using one or more vector registers: A method for managing multiple values assigned to a variable during various stages of a software pipelined process executed in a computing environment. The method comprises allocating two or more slots in a vector register to two or more values associated with said variable during two or more stages of... Agent: Ibm Corporation, T.j. Watson Research Center
20090113169 - Reconfigurable array processor for floating-point operations: A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in... Agent: Fish & Richardson, PC
20090113170 - Apparatus and method for processing an instruction matrix specifying parallel and dependent operations: A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.... Agent: Cooley Godward Kronish LLP Attn: Patent Group
20090113172 - Network topology for a scalable multiprocessor system: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20090113171 - Tpm device for multi-processor systems: In one embodiment, a computer system comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, at least one programmable trusted platform management device coupled to the processor via a hardware path which goes through at least one trusted platform... Agent: Hewlett Packard Company
20090113173 - Computer system and method that eliminates the need for an operating system: A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM... Agent: Wilmerhale/new York
20090113174 - Sign operation instructions and circuitry: A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value... Agent: Texas Instruments Incorporated
20090113175 - Processor architecture for concurrently fetching data and instructions: In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated... Agent: Farjami & Farjami LLP
20090113176 - Method of reducing data path width restrictions on instruction sets: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP
20090113180 - Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor: A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090113177 - Integrated circuit with dma module for loading portions of code to a code memory for execution by a host processor that controls a video decoder: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases... Agent: Christopher C. Winslade, Esq. Mcandrews, Held & Malloy, Ltd.
20090113178 - Microprocessor based on event-processing instruction set and event-processing method using the same: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore,... Agent: Staas & Halsey LLP
20090113179 - Operational processing apparatus, processor, program converting apparatus and program: The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus synchronizes with a hardware accelerator. A processor in the present invention simultaneously issues and executes instructions including instruction groups having a simultaneously issueable instruction. The... Agent: Greenblum & Bernstein, P.L.C
20090113181 - Method and apparatus for executing instructions: A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090113182 - System and method for issuing load-dependent instructions from an issue queue in a processing unit: A system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. In response to a LSU determining that a load request from a load instruction missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry... Agent: Dillon & Yudell LLP
20090113183 - Method of controlling a device and a device controlled thereby: A method of controlling at least one device is disclosed. The method includes providing the device with at least one constraint for carrying out an operation. The device determines if the constraint can be met. If it is determined that the constraint can be met, the device determines on its... Agent: Agilent Technologies Inc.
20090113184 - Method, apparatus, and program for pinning internal slack nodes to improve instruction scheduling: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090113185 - Processor for executing multiply matrix and convolve extract instructions requiring wide operands: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP
20090113186 - Microcontroller and controlling system: A microcontroller and a controlling system having the same are provided, in which the increase in the program code for performing floating-point arithmetic, in particular, the increase in the amount of code due to a variable are suppressed, and the processing overhead for converting fixed-point data into floating-point data is... Agent: Miles & Stockbridge PC
20090113188 - Coordinator server, database server, and pipeline processing control method: A first transmitting unit transmits a processing command to a plurality of parallelized database servers. A second transmitting unit integrates data sets transmitted from the database servers in response to the processing command, and transmits an integrated data set to a client. An integrating unit integrates data sets buffered in... Agent: Amin, Turocy & Calvin, LLP
20090113187 - Processor architecture for executing instructions using wide operands: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP
20090113189 - Method and system for hiding information in the instruction processing pipeline: A system, article of manufacture and method is provided for transferring secret information from a first location to a second location. The secret information is encoded and stalls in executable code are located. The executable code is configured to perform a predetermined function when executed on a pipeline processor. The... Agent: Law Office Of Donald L. Wenskay
20090113190 - Gathering operational metrics within a grid environment using ghost agents: A method for gathering operational metrics can include the step of identifying a host within a grid environment, wherein the host can be a software object. A ghost agent can be associated with the host. The ghost agent can replicate actions of the host. Operational metrics for at least a... Agent: Novak Druce + Quigg LLP
20090113191 - Apparatus and method for improving efficiency of short loop instruction fetch: A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short... Agent: Dillon & Yudell LLP
20090113192 - Design structure for improving efficiency of short loop instruction fetch: A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction... Agent: Dillon & Yudell LLP04/23/2009 > patent applications in patent subcategories.
20090106525 - Design structure for scalar precision float implementation on the \"w\" lane of vector unit: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for image processing, and more specifically to vector units for supporting image processing is provided. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090106526 - Scalar float register overlay on vector register file for efficient register allocation and scalar float and vector register sharing: Embodiments of the invention are generally related to image processing, and more specifically to register files for supporting image processing. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090106527 - Scalar precision float implementation on the \"w\" lane of vector unit: Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090106528 - Parallel image processing system control method and apparatus: To reduce the required amount of program codes when processing the whole image in a one-dimensional SIMD parallel image processing system having a smaller number of PEs than the number of pixels in the width direction of the image to be processed. A controller for controlling a PE array includes... Agent: Foley And Lardner LLP Suite 500
20090106529 - Flattened butterfly processor interconnect network: A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.... Agent: Schwegman, Lundberg & Woessner, P.A.
20090106530 - System, method, and computer program product for generating a ray tracing data structure utilizing a parallel processor architecture: A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is... Agent: Zilka-kotab, PC
20090106531 - Field programmable gate array and microcontroller system-on-a-chip: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a... Agent: Lewis And Roca LLP
20090106532 - Rapid creation and configuration of microcontroller products with configurable logic devices: Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090106533 - Data processing apparatus: The data processing apparatus includes two or more execution resources, each enabling a predetermined process for executing an instruction. The execution resources enable a pipeline process. Each execution resource treats instructions according to an in-order system following the instructions' flow order in case that the execution resource is in charge... Agent: Miles & Stockbridge PC
20090106534 - System and method for implementing a software-supported thread assist mechanism for a microprocessor: A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch unit (IDU) places the first thread into a sleep mode. The IDU separates an... Agent: Dillon & Yudell LLP
20090106536 - Processor for executing group extract instructions requiring wide operands: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP
20090106537 - Processor supporting vector mode execution: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether,... Agent: Stmicroelectronics, Inc.
20090106535 - Shared processor architecture applied to functional stages configured in a receiver system for processing signals from different transmitter systems and method thereof: According to an embodiment of the present invention, a shared processor architecture in a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system... Agent: North America Intellectual Property Corporation
20090106538 - System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor: The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode... Agent: Dillon & Yudell LLP
20090106539 - Method and system for analyzing a completion delay in a processor using an additive stall counter: In a data processing system having a set of components for performing a set of operations, in which one or more of the set of operations has processing dependencies with respect to other of the set of operations, a method for using an additive stall counter to analyze a completion... Agent: Dillon & Yudell LLP
20090106540 - Apparatus and method for remanipulating instructions: An apparatus for modifying instructions of a machine readable program according to remanipulation rules includes a remanipulation unit, which is configured to identify a manipulated instruction and to remanipulate the manipulated instruction according the remanipulation rules. The apparatus further includes a processor unit configured to process a predetermined instruction set,... Agent: Dickstein Shapiro LLP
20090106541 - Processors with branch instruction, circuits, systems and processes of manufacture and operation: An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at... Agent: Texas Instruments Incorporated04/16/2009 > patent applications in patent subcategories.
20090100247 - Simd permutations with extended range in a data processor: A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first source register stores at least one in-range index value for the at least one other source register and at least one... Agent: Freescale Semiconductor, Inc. Law Department
20090100248 - Hierarchical system, and its management method and program: A lower system structure reports performance information to an upper system structure. When detecting performance deterioration of the system structure on the basis of the reported performance information, the upper system structure optimizes resource redistribution of the system structure that the upper system structure manages. If the performance is improved... Agent: Scully Scott Murphy & Presser, PC
20090100249 - Method and apparatus for allocating architectural register resources among threads in a multi-threaded microprocessor core: One embodiment of a microprocessor core capable of executing a plurality of threads substantially simultaneously includes a plurality of register resources available for use by the threads, where the register resources are fewer in number than the number threads multiplied by a number of architectural register resources required per thread,... Agent: Patterson & Sheridan LLP IBM Corporation
20090100250 - Switching between multiple software entities using different operating modes of a processor: The computer program includes a virtualization software that is executable on the new processor in the legacy mode. The new processor includes a legacy instruction set for a legacy operating mode and a new instruction set for a new operation mode. The switching includes switching from the new instruction set... Agent: Vmware, Inc.
20090100251 - Parallel context adaptive binary arithmetic coding: A method for performing parallel processing of at least two bins in an arithmetic coded bin stream includes: utilizing a current range to calculate a range for a first bin in the bin stream; simultaneously utilizing the current range to forward predict a plurality of possible ranges and low values... Agent: North America Intellectual Property Corporation
20090100252 - Vector processing system: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of... Agent: Mcandrews Held & Malloy, Ltd
20090100253 - Methods for performing extended table lookups: A permutation instruction generates vector elements for a destination register using identified source and destination registers. A plurality of partial table lookups corresponding to an extended table produces a plurality of intermediate results. At least one source register stores a plurality of index values corresponding to the extended table. Out-of-range... Agent: Freescale Semiconductor, Inc. Law Department
20090100254 - Debug instruction for use in a data processing system: A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be... Agent: Freescale Semiconductor, Inc. Law Department
20090100255 - Guaranteed core access in a multiple core processing system: Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction, or by a routine. Once granted, the access provides exclusive access to... Agent: Scott C Harris04/09/2009 > patent applications in patent subcategories.
20090094436 - Ultra-scalable supercomputer based on mpu architecture: The invention provides an ultra-scalable supercomputer based on MPU architecture in achieving the well-balanced performance of hundreds of TFLOPS or PFLOPS range in applications. The supercomputer system design includes the interconnect topology and its corresponding routing strategies, the communication subsystem design and implementation, the software and hardware schematic implementations. The... Agent: William H. Honaker Dickinson Wright PLLC
20090094437 - Method and device for controlling multicore processor: The present invention provides a method and a device for controlling a multicore processor by selecting and operating the appropriate number of cores corresponding to an operation state of the processor. In a multicore processor having a plurality of cores each independently performing a calculation process on one processor, an... Agent: Alpine/bhgl
20090094438 - Over-provisioned multicore processor: An over-provisioned multicore processor employs more cores than can simultaneously run within the power envelope of the processor, enabling advanced processor control techniques for more efficient workload execution, despite significantly decreasing the duty cycle of the active cores so that on average a full core or more may not be... Agent: Wisconsin Alumni Research Foundation
20090094439 - Data processing apparatus and method employing multiple register sets: A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a... Agent: Nixon & Vanderhye, PC
20090094440 - Pre-fetch circuit of semiconductor memory apparatus and control method of the same: A pre-fetch circuit of a semiconductor memory apparatus can carry out a high-frequency operating test through a low-frequency channel of a test equipment. The pre-fetch circuit of a semiconductor memory apparatus can includes: a pre-fetch unit for pre-fetching data bits in a first predetermined number; a plurality of registers provided... Agent: Baker & Mckenzie LLP Patent Department
20090094441 - Perform floating point operation instruction: A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprise the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit has a first value, (a) a... Agent: Scully, Scott, Murphy & Presser, P.C.
20090094442 - Storage medium storing load detecting program and load detecting apparatus: A load detecting apparatus includes a load controller, and judges a motion of a player on the basis of detected load values. Judgment timing for a motion of putting the feet on and down from the controller is decided on the basis of an elapsed time from an instruction of... Agent: Nixon & Vanderhye, P.C.
20090094443 - Information processing apparatus and method thereof, program, and storage medium: An information processing apparatus includes a determining unit adapted to determine a target instruction to be modified to a camouflaged instruction among instructions contained in a processing target program, a camouflaged instruction generating unit adapted to generate the camouflaged instruction corresponding to the target instruction, a restore command generating unit... Agent: Fitzpatrick Cella Harper & Scinto
20090094444 - Link stack repair of erroneous speculative update: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the... Agent: Qualcomm Incorporated
20090094445 - Process retext for dynamically loaded modules: A computer implemented method, apparatus, and computer program product for dynamically loading a module into an application address space. In response to receiving a checkpoint signal by a plurality of threads associated with an application running in a software partition, the plurality of threads rendezvous to a point outside an... Agent: Ibm Corp (ya) C/o Yee & Associates PC04/02/2009 > patent applications in patent subcategories.
20090089551 - Apparatus and method of avoiding bank conflict in single-port multi-bank memory system: Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing... Agent: Staas & Halsey LLP
20090089552 - Dependency graph parameter scoping: A number of tasks are defined according to a dependency graph. Multiple parameter contexts are maintained, each associated with a different scope of the tasks. A parameter used in a first of the tasks is bound to a value. This binding includes identifying a first of the contexts according to... Agent: Fish & Richardson PC
20090089554 - Method for tuning chipset parameters to achieve optimal performance under varying workload types: A method, system, and computer program product for tuning a set of chipset parameters to achieve optimal chipset performance under varying workload characteristics. A set of workload characteristics of a current workload type is determined. An instruction stream is generated using weighted parameters derived from the set of workload characteristics... Agent: Ibm Corporation
20090089555 - Methods and apparatus for executing or converting real-time instructions: In one embodiment, a computer processor is configured to execute a plurality of instructions defined by an instruction set including at least one real-time instruction. Each of the at least one real-time instruction specifies an execution timing of a respective one of the at least one real-time instruction. Each execution... Agent: Agilent Technologies Inc.
20090089553 - Multi-threaded processing: A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.
20090089556 - High-speed add-compare-select (acs) circuit: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately... Agent: Texas Instruments Incorporated
20090089557 - Utilizing masked data bits during accesses to a memory: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a... Agent: Pvf -- Rambus, Inc. C/o Park, Vaughan & Fleming, LLP
20090089558 - Adjustment of data collection rate based on anomaly detection: Systems and methods that vary multiple data sampling rates, to collect sets of data with different levels of granularity for an industrial system. The data for such industrial system includes sets of data from the “internal” data stream(s) (e.g., history data collected from an industrial unit) and sets of data... Agent: Amin Turocy & Calvin, LLP Attention: Heather Holmes
20090089559 - Method of managing data movement and cell broadband engine processor using the same: A method of managing data movement in a cell broadband engine processor, comprising: determining one or more idle synergistic processing elements among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a... Agent: Ibm Corporation, (olp) C/o Ortiz & Lopez, PLLCPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.14901 seconds