|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) March listing by industry category 03/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/26/2009 > patent applications in patent subcategories.
20090083516 - Multimedia processing in parallel multi-core computation architectures: In a media server for processing data packets, media server functions are implemented by a plurality of modules categorized by real-time response requirements.... Agent: Marks & Clerk
20090083515 - Soft-reconfigurable massively parallel architecture and programming system: In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next... Agent: Tue Nguyen
20090083518 - Attaching and virtualizing reconfigurable logic units to a processor: In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled... Agent: Trop, Pruner & Hu, P.C.
20090083517 - Lockless processing of command operations in multiprocessor systems: A beltway mechanism that takes advantage of atomic locking mechanisms supported by certain classes of hardware processors to handle the tasks that require atomic access to data structures while also reducing the overhead associated with these atomic locking mechanisms. The beltway mechanisms described herein can be used to control access... Agent: Baker Botts L.L.P.
20090083519 - Processing element (pe) structure forming floating point-reconfigurable array (fp-ra) and fp-ra control circuit for controlling the fp-ra: Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing... Agent: Fish & Richardson, PC
20090083520 - Data processing device: Provided is a data processing device that can prevent data used by a program from being used by another program in an unauthorized manner, regardless of the quality of the programs. The data processing device includes: a CPU 0201 for executing programs; and an unauthorized operation prevention circuit 0105 that... Agent: Wenderoth, Lind & Ponack L.L.P.
20090083523 - Processor power management associated with workloads: Some embodiments provide determination of a processor performance characteristic associated with a first workload, and determination of a processor performance state for the first workload based on the performance characteristic. Further aspects may include determination of a second processor performance characteristic associated with a second workload, determination of a second... Agent: Buckley, Maschoff & Talwalkar LLC
20090083521 - Program illegiblizing device and method: A program obfuscating device for generating obfuscated program from which unauthorized analyzer cannot obtain confidential information easily. The program obfuscating device stores original program that contains authorized program instructions and confidential process instruction group containing confidential information that needs to be kept confidential, generates process instructions which, when executed in... Agent: Wenderoth, Lind & Ponack L.L.P.
20090083522 - Systems, devices, and/or methods for managing programmable logic controller processing: Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive to a received request to process a Boolean operation, execute a single processor data access instruction addressed to a region of a memory-mapped... Agent: Siemens Corporation Intellectual Property Department
20090083524 - Programmable data processing circuit that supports simd instruction: A data processing circuit contains an instruction execution circuit (12b) that has an instruction set that comprises a SIMD instruction. The instruction execution circuit comprises a plurality of arithmetic circuits (26a-d), arranged to perform N respective identical operations in parallel in response to the SIMD instruction. The SIMD instruction defines... Agent: Philips Intellectual Property & Standards
20090083525 - Systems and methods that facilitate management of add-on instruction generation, selection, and/or monitoring during execution: The subject invention relates to systems and methods that facilitate display, selection, and management of context associated with execution of add-on instructions. The systems and methods track add-on instruction calls provide a user with call and data context, wherein the user can select a particular add-on instruction context from a... Agent: Amin Turocy & Calvin, LLP Attention: Heather Holmes
20090083526 - Program conversion apparatus, program conversion method, and comuter product: A linker generates a simulator-use executable format program from a pre-conversion object program and a simulator-use object program. A simulator executes the simulator-use object program and acquires branch trace information. A binary program converting tool, based on the branch trace information and a branch penalty table, generates a post-conversion object... Agent: Staas & Halsey LLP
20090083527 - Counter circuit, dynamic reconfigurable circuitry, and loop processing control method: A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context,... Agent: Staas & Halsey LLP03/19/2009 > patent applications in patent subcategories.
20090077345 - Simd dot product operations with overlapped operands: A data processing system includes a plurality of general purpose registers, and processor circuitry for executing one or more instructions, including a vector dot product instruction for simultaneously performing at least two dot products. The vector dot product instruction identifies a first and second source register, each for storing a... Agent: Freescale Semiconductor, Inc. Law Department
20090077346 - Processing module, processor circuit, instruction set for processing data, and method for synchronizing the processing of codes: A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The... Agent: Dickstein Shapiro LLP
20090077347 - Systems and methods for wake on event in a network: Embodiments include systems and methods for allowing a host CPU to sleep while service presence packets and responses to search requests are sent by an alternate processor. While the CPU is in a low power state, the alternate processor monitors the network for incoming request packets. Also, while the CPU... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC
20090077348 - Providing a dedicated communication path for compliant sequencers: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a... Agent: Trop, Pruner & Hu, P.C.
20090077349 - Method of managing instruction cache and processor using the method: A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during the inactive mode, wherein... Agent: Mcneely Bodendorf LLP
20090077350 - Data processing system and method: A method, system and computer program for modifying an executing application, comprising monitoring the executing application to identify at least one of a hot load instruction, a hot store instruction and an active prefetch instruction that contributes to cache congestion; where the monitoring identifies a hot load instruction, enabling at... Agent: Hewlett Packard Company
20090077351 - Information processing device and compiler: Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of... Agent: Ibm Corporation, T.j. Watson Research Center
20090077352 - Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines: A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.
20090077353 - Programming language type system with automatic conversions: A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a... Agent: Lahive & Cockfield, LLP/the Mathworks Floor 30, Suite 3000
20090077354 - Techniques for predicated execution in an out-of-order processor: A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.... Agent: Dillon & Yudell LLP
20090077355 - Instruction exploitation through loader late fix up: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090077356 - Load time instruction substitution: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090077357 - Method of power simulation and power simulator: Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the second instruction; a dynamic information extracting unit that extracts dynamic information with respect to the execution of the second instruction;... Agent: Mcneely Bodendorf LLP
20090077359 - Architecture re-utilizing computational blocks for processing of heterogeneous data streams: An architecture for heterogeneous data processing which reuses the same hardware to process different data in different manners is disclosed. The different processing has a substantial similarity; such as performing different variations of a computation. For example, the computation may involve the same mathematical operations but use different constants or... Agent: Hickman Palermo Truong & Becker / Tessera Inc.
20090077360 - Software constructed stands for execution on a multi-core architecture: In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG... Agent: Trop, Pruner & Hu, P.C.
20090077361 - Detecting spin loops in a virtual machine environment: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the... Agent: Intel Corporation C/o Intellevate, LLC03/12/2009 > patent applications in patent subcategories.
20090070548 - Programming a digital processor with a single connection: A digital processor is coupled to a processor programmer through a single programming connection (e.g., terminal, pin, etc.) coupled to the single conductor programming bus. The processor programmer comprises an instruction encoder/decoder, a Manchester encoder, a Manchester decoder, a bus receiver and a bus transmitter. The digital processor comprises an... Agent: Baker Botts L.L.P. One Shell Plaza
20090070549 - Interconnect architecture in three dimensional network on a chip: The connection architecture of a network on a chip (NoC) is described in which (a) nodes in octahedron sections are connected in an arc Benes network, (b) a hierarchy of node clusters are connected using a globally asynchronous locally asynchronous (GALA) configuration, (c) a double wishbone 2D torus ring is... Agent: Neal Solomon
20090070550 - Operational dynamics of three dimensional intelligent system on a chip: The invention pertains to a 3D intelligent SoC. The self-regulating data flow mechanisms of the 3D SoC are elucidated, particularly parallelization of multiple asynchronous 3D IC nodes and reconfigurable components. These behavioral mechanisms are organized into a polymorphous computing architecture with plasticity functionality. Software agents are employed for reprogrammable 3D... Agent: Neal Solomon
20090070551 - Creation of logical apic id with cluster id and intra-cluster id: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical... Agent: Alan K. Aldous Intel Corporation
20090070552 - Reconfigurable multi-processing coarse-grain array: A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of... Agent: Knobbe Martens Olson & Bear LLP
20090070553 - Dispatch mechanism for dispatching insturctions from a host processor to a co-processor: A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to... Agent: Fulbright & Jaworski L.l.p
20090070555 - Device and method for finding extreme values in a data block: A method for locating an extreme value data chunk within a data block, the method includes: fetching, by a processor, an instruction; fetching, in response to a content of the instruction, a data unit that comprises multiple data chunks; selectively masking the fetched data chunks in response to a value... Agent: Freescale Semiconductor, Inc. Law Department
20090070554 - Register file system and method for pipelined processing: The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a... Agent: Qualcomm Incorporated
20090070556 - Store stream prefetching in a microprocessor: In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in... Agent: Dillon & Yudell LLP
20090070557 - Parallel program execution of command blocks using fixed backjump addresses: The invention relates to a method for executing instructions in a processor, according to which an instruction to be executed of a program memory is addressed by a program control unit by means of a program counter reading of a program counter that operates in said unit. The addressed instruction... Agent: Baker Botts L.L.P.
20090070558 - Multiplexing per-probepoint instruction slots for out-of-line execution: The present invention provides a probe system and method for multithreaded user-space programs. The system includes an instrumentation module that enables single stepping out of line processing for multithreaded programs, an establish probepoint module that divides up an area of the probed program's memory into a plurality of instruction slots,... Agent: Cantor Colburn LLP - IBM Tuscon Division
20090070559 - Data processing circuit wherein functional units share read ports: A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21 a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled to a respective one of the write ports for writing... Agent: Philips Intellectual Property & Standards
20090070560 - Method and apparatus for accelerating the access of a multi-core system to critical resources: A method accelerates access of a multi-core system to its critical resources, which includes preparing to delete a critical node in a critical resource, separating the critical node from the critical resource, and deleting the critical node if the conditions for deleting the critical node are satisfied. An apparatus includes... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20090070561 - Link stack misprediction resolution: Illustrative embodiments provide a method for improved link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090070562 - Method and apparatus for assigning thread priority in a processor or the like: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier... Agent: Kenyon & Kenyon LLP
20090070563 - Concurrent physical processor reassignment: Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another physical processor, such that the logical processor is backed by a different physical processor. This reassignment is performed concurrent to processor... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20090070564 - Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed: Aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method of operating duplicate copies of a user program in a first and second processor, allowing at least one of the user programs to... Agent: Hewlett Packard Company
20090070566 - Electronic device with cpu and interrupt relay stage: An electronic device with a CPU configured to be switched from a low power mode into a higher power mode in response to an interrupt and an interrupt relay coupled between an interrupt generator and the CPU. A functional stage is coupled to the interrupt relay and functionally linked with... Agent: Texas Instruments Incorporated
20090070565 - Methods, systems, computer programs and apparatus for changing a processor state: Methods, systems, computer programs and apparatus for changing a processor state. In example embodiments of the invention, software porting onto an operating system calls a library routine, which creates an illegal instruction for special values in parameter registers. An illegal instruction exception handler recognizes the illegal instructions for special values... Agent: Fitzpatrick Cella Harper & Scinto
20090070567 - Efficient implementation of branch intensive algorithms in vliw and superscalar processors: An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at... Agent: Patent Group 2n Jones Day
20090070568 - Computation parallelization in software reconfigurable all digital phase lock loop: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner.... Agent: Texas Instruments Incorporated
20090070569 - Branch prediction device,branch prediction method, and microprocessor: A branch prediction device predicts a branching probability in which a branch condition of a conditional branch instruction read out from an instruction memory storing an instruction is satisfied. A branch prediction entry part included in the branch prediction device stores prediction information as to whether or not the branch... Agent: Sughrue Mion, PLLC
20090070570 - System and method for efficiently handling interrupts: A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt,... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen03/05/2009 > patent applications in patent subcategories.
20090063811 - System for data processing using a multi-tiered full-graph interconnect architecture: A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes.... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090063812 - Processor, data transfer unit, multicore processor system: A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data... Agent: Miles & Stockbridge PC
20090063813 - Method and system for flexible and negotiable exchange of link layer functional parameters: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090063817 - System and method for packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture: A method, computer program product, and system are provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data to be transmitted to a destination processor, the original data provided by a first source processor. The first processor transmits the bundle of data... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090063816 - System and method for performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture: A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090063815 - System and method for providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture: A method, computer program product, and system are provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090063814 - System and method for routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture: A method, computer program product, and system are provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090063818 - Alignment of cache fetch return data relative to a thread: A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of... Agent: Ryan, Mason & Lewis, LLP
20090063819 - Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.
20090063820 - Application specific instruction set processor for digital radio processor receiving chain signal processing: This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each... Agent: Texas Instruments Incorporated
20090063822 - Microprocessor: A microprocessor includes: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a specific instruction; and a memory that temporary stores the instruction with the analysis information,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090063821 - Processor apparatus including operation controller provided between decode stage and execute stage: A processor apparatus includes a sequence controller that decodes the instruction code stored in an instruction memory, an operation array that executes operation of the decoded instruction code, and an asynchronous FIFO. The asynchronous FIFO is provided between a decode stage for decoding the instruction code into at least one... Agent: Mcdermott Will & Emery LLP
20090063824 - Compound instructions in a multi-threaded processor: A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the thread and includes a further register shared by all the... Agent: Flynn Thiel Boutell & Tanis, P.C.
20090063823 - Method and system for tracking instruction dependency in an out-of-order processor: A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions... Agent: Dillon & Yudell LLP
20090063826 - Quad aware locking primitive: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock,... Agent: Lieberman & Brandsdorfer, LLC
20090063825 - Systems and methods for compressing state machine instructions: Systems and methods for compressing state machine instructions are disclosed herein. In one embodiment, the method comprises associating input characters associated with states to respective indices, where each index comprises information indicative of a particular transition instruction.... Agent: Knobbe Martens Olson & Bear LLP
20090063827 - Parallel processor and arithmetic method of the same: A parallel processor includes a fetch unit configured to hold a processor instruction having a composite arithmetic instruction with repeat designation and a sync instruction, a decoder unit configured to decode the processor instruction, a plurality of pipeline arithmetic units configured to execute arithmetic operations parallel on the basis of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090063828 - Systems and methods for communication between a pc application and the dsp in a hda audio codec: Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes... Agent: Law Offices Of Mark L. Berrier
20090063830 - Debugging mechanism for a processor, arithmetic operation unit and processor: A debugging mechanism equipped within a processor and receiving, as inputs, respective pieces of arithmetic operation data related to a plurality of arithmetic units comprised within the processor, and receiving, as inputs, respective control signals used for the respective arithmetic operations, comprising: an unit which comprises a counter performing a... Agent: Staas & Halsey LLP
20090063829 - Method, system, computer program product and data processing program for verifying a processor design: An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the... Agent: Ibm Corporation
20090063831 - Branch predictor for branches with asymmetric penalties: A mechanism is disclosed for enabling a plurality of nodes on a network to collaboratively exchange sets of rendering information respecting a file. In one implementation, each node maintains its own copy of the file, and each node may access its copy of the file. Whenever a node does access... Agent: Hickman Palermo Truong & Becker, LLP And Sun Microsystems, Inc.
20090063832 - Fault discovery and selection apparatus and method: A method and apparatus are disclosed for discovering and selecting faults where more than one programming model is involved. The present invention enables selection of faults and the mappings necessary to handle exceptions across multiple code environments.... Agent: Kunzler & MckenziePrevious industry: Electrical computers and digital processing systems: memory
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