|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
02/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) February patent applications/inventions, industry category 02/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/26/2009 > patent applications in patent subcategories.
20090055624 - Control of processing elements in parallel processors: The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090055625 - Parallel processing systems and method: Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the... Agent: Lathrop & Gage Lc
20090055627 - Efficient pipeline parallelism using frame shared memory: A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by... Agent: Townsend And Townsend And Crew, LLP
20090055626 - Method of sharing coarse grained array and processor using the method: A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a... Agent: Mcneely Bodendorf LLP
20090055628 - Methods and computer program products for reducing load-hit-store delays by assigning memory fetch units to candidate variables: Assigning each of a plurality of memory fetch units to any of a plurality of candidate variables to reduce load-hit-store delays, wherein a total number of required memory fetch units is minimized. A plurality of store/load pairs are identified. A dependency graph is generated by creating a node Nx for... Agent: Cantor Colburn LLP - IBM Austin
20090055629 - Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor: An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determination logic which compares concatenate bits of a first N-bit... Agent: Bacon & Thomas, PLLC
20090055631 - Method and apparatus for register renaming using multiple physical register files and avoiding associative search: A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of... Agent: Cantor Colburn LLP-ibm Yorktown
20090055630 - Program processing device, parallel processing program, program processing method, parallel processing compiler, recording medium containing the parallel processing compiler, and multi-processor system: In a multi-processor system for performing a parallel processing, each of a plurality of processors includes a communication processing unit for performing control between the processors in a data flow machine-type data-driven control method; and a program processing unit for performing control in each processor in a Neumann-type program-driven control... Agent: Fenwick & West LLP
20090055632 - Emulation scheme for programmable pipeline fabric: The present invention allows emulation of a programmable pipeline processor fabric or architecture. According to certain aspects, the invention permits real-time capture of state information for any given stage of a processing flow performed by the fabric or architecture. According to other aspects, the invention allows a particular stage and... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090055634 - Compiling method, apparatus, and program: Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining... Agent: Ibm Corporation, T.j. Watson Research Center
20090055633 - Computer processing system employing an instruction reorder buffer: A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after... Agent: Cantor Colburn LLP-ibm Yorktown
20090055635 - Program execution control device: A program execution control device which controls execution of a program by a processor having a predicate function for conditional execution of an instruction, wherein the program includes a branch instruction to control iterations in loop processing, the branch instruction is further an instruction to generate an execute-or-not condition indicating... Agent: Greenblum & Bernstein, P.L.C
20090055636 - Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence: A computer implemented method, data processing system, and computer program product for generating and applying a model to predict hardware performance hazards in a machine instruction sequence. The illustrative embodiments generate rules which specify relationships between a first instruction code sequence and hardware performance hazards. This rule generation is performed... Agent: Duke W. Yee02/19/2009 > patent applications in patent subcategories.
20090049275 - Processing elements, mixed mode parallel processor system, processing method by processing elements, mixed mode parallel processor method, processing program by processing elements and mixed mode parallel processing program: Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the... Agent: Scully Scott Murphy & Presser, PC
20090049276 - Techniques for sourcing immediate values from a vliw: Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded... Agent: Murabito Hao & Barnes LLP
20090049277 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is provided. The operating frequency generating component generates an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates. The extracting component extracts a critical path that is the slowest path when a... Agent: Volentine & Whitt PLLC
20090049278 - Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU),... Agent: Dillon & Yudell LLP
20090049279 - Thread interleaving in a multithreaded embedded processor: The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction... Agent: Mr. John Garred Tucker Ellis & West
20090049280 - Software controlled cpu pipeline protection: A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while executing instructions and sets a pipeline protection mode in accordance with the directive. The processor then continues to fetch and execute instructions in an unprotected manner if the pipeline... Agent: Texas Instruments Incorporated
20090049281 - Multimedia decoding method and multimedia decoding apparatus based on multi-core processor: Provided are a multimedia decoding method and multimedia decoding apparatus based on a multi-core platform including a central processor and a plurality of operation processors. The multimedia decoding method includes performing a queue generation operation on input multimedia data to generate queues of one or more operations of the multimedia... Agent: Sughrue Mion, PLLC
20090049282 - System and method for managing data: A method of performing data and pointer compression includes, in a buffer which is formed between a processor and a level one cache and stores plural tags and full-word values associated with the tags, when the buffer is presented with an address, breaking the address into a line number which... Agent: Mcginn Intellectual Property Law Group, PLLC
20090049283 - Information processing device and instruction executing method: An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register. The information processing device can issue an inter-register copy instruction for instructing data held in one register to be copied to another... Agent: Nec Corporation Of America
20090049285 - Information delivery apparatus, information reproduction apparatus, and information processing method: An information delivery apparatus includes an encoding information collection unit which collects information used to encode content information, a generation unit which predicts decode processes of the content information based on the collected information, and generates configuration information used to configure data paths required to execute the decode processes, an... Agent: Fitzpatrick Cella Harper & Scinto
20090049284 - Parallel subword instructions with distributed results: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position... Agent: Hewlett Packard Company
20090049286 - Data processing system, processor and method of data processing having improved branch target address cache: A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC)... Agent: Dillon & Yudell LLP
20090049287 - Stall-free pipelined cache for statically scheduled and dispatched execution: This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention... Agent: Texas Instruments Incorporated
20090049288 - System, method, and computer program product for runtime invocation of an appropriate version of program instructions in an on-demand database: In accordance with embodiments, there are provided mechanisms and methods for runtime invocation of an appropriate version of program instructions in an on-demand database service. These mechanisms and methods for providing such runtime invocation can enable embodiments to ensure that new versions of developed applications will operate in the same... Agent: Zilka-kotab, PC02/12/2009 > patent applications in patent subcategories.
20090043986 - Processor array system with data reallocation function among high-speed pes: A processor array system which is able to perform load balancing among PEs at high speed is provided. When an instruction code 113, “MVLR”, is sent from a control processor 110, in a PE having a mask register MR being in operation setting, in case wherein the direction register F... Agent: Foley And Lardner LLP Suite 500
20090043987 - Operation distribution method and system using buffer: Provided is an operation distribution method and system using a buffer. The operation distribution system includes a buffer, a first operation device performing a first operation and storing a result of the first operation performed by the first operation device in the buffer, and a second operation device performing a... Agent: Staas & Halsey LLP
20090043988 - Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks: Methods, apparatus, and products are disclosed for configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks, the compute nodes in the operational group connected together for data communications through a global combining network, that include: partitioning the compute nodes in... Agent: Ibm (roc-blf)
20090043990 - Implementation of variable length instruction encoding using alias addressing: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second... Agent: Wolf Greenfield & Sacks, P.C.
20090043989 - Null value checking instruction: A processor 2 is provided with the ability to execute program instructions in the form of Java bytecodes including a dedicated null checking instruction. The null checking instruction reads the top of stack value, compares this with a null value and jumps to an exception handling routine if the top... Agent: Nixon & Vanderhye, PC
20090043992 - Method and system for data speculation on multicore systems: The method and system for data speculation of multicore systems are disclosed. In one embodiment, a method includes dynamically determining whether a current speculative load instruction and an associated store instruction have same memory addresses in an application thread in compiled code running on a main core using a dynamic... Agent: Hewlett Packard Company
20090043993 - Monitoring values of signals within an integrated circuit: An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of... Agent: Nixon & Vanderhye P.C.
20090043994 - Resource flow computer: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are... Agent: Connolly Bove Lodge & Hutz LLP
20090043991 - Scheduling multithreaded programming instructions based on dependency graph: A computer implemented method for scheduling multithreaded programming instructions based on the dependency graph wherein the dependency graph organizes the programming instruction logically based on blocks, nodes, and super blocks and wherein the programming instructions could be executed outside of a critical section may be executed outside of the critical... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090043995 - Handling data cache misses out-of-order for asynchronous pipelines: An apparatus and method for handling data cache misses out-of-order for asynchronous pipelines are provided. The apparatus and method associates load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090043996 - User co-routine interface for customizing sip and sdp protocols: A method of using co-routines to implement a function-like interface between a BASIC program and the points in the system where SIP and SDP data (for example) are to be modified. This co-routine interface is intuitive from the end-user's perspective, and both real-time efficient and flexible from the system designer's... Agent: Harris Beach PLLC
20090043997 - Time-of-life counter for handling instruction flushes from a queue: Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen02/05/2009 > patent applications in patent subcategories.
Previous industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.05122 seconds