|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All |
01/2009 | Recent | 15: Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) January recently filed with US Patent Office 01/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/29/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090031103 - Mechanism for implementing a microcode patch during fabrication: A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated patch records that are employed to patch microcode or circuits in the microprocessor. The array controller is coupled to... Agent: Huffman Law Group, P.c.
20090031104 - Low latency massive parallel data processing device: Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.... Agent: Kenyon & Kenyon LLP
20090031105 - processor for executing group instructions requiring wide operands: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP
20090031106 - Reconfigurable device: There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing blocks. Each processing block (13) includes a logic operation unit (21) whose... Agent: Marshall, Gerstein & Borun LLP
20090031108 - Configurable fuse mechanism for implementing microcode patches: A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to... Agent: Huffman Law Group, P.c.
20090031107 - On-chip memory providing for microcode patch overlay and constant update functions: A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding... Agent: Huffman Law Group, P.c.
20090031109 - Apparatus and method for fast microcode patch from memory: A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a... Agent: Huffman Law Group, P.c.
20090031110 - Microcode patch expansion mechanism: A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM.... Agent: Huffman Law Group, P.c.
20090031111 - Method, apparatus and computer program product for dynamically selecting compiled instructions: A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states... Agent: Cantor Colburn LLP-ibm Burlington
20090031112 - System and method for providing global variables within a human capital management system: A system and method are provided for stacking global variables associated with a plurality of tools. The method includes loading a first tool global variable into a memory and executing a first tool of a computer application, the computer application configured to automate human resource processes. The method includes responsive... Agent: Kenyon & Kenyon LLP
20090031113 - Processor array, processor element complex, microinstruction control appraratus, and microinstruction control method: A processor array including area-saving microprogram memories is provided. In the processor array, microprogram memories of a plurality of adjacent processor arrays are shared. Effective data and position information 13 on the effective data are stored in the shared microprogram memory 3, and effective data parts 11.1 to 11.3 including... Agent: Foley And Lardner LLP Suite 500
20090031114 - Multithread processor: To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is... Agent: Miles & Stockbridge Pc
20090031115 - Method for high integrity and high availability computer processing: A method of providing high integrity checking for an N-lane computer processing module (Module), N being an integer greater than equal to two. The method comprises the steps of: detecting, by a data Output Management unit (OM), when any of the N processing lanes sends different output data; configuring each... Agent: General Electric Company Global Research
20090031117 - Same instruction different operation (sido) computer with short instruction and provision of sending instruction code through data: A same instruction different operation (SIDO) processor is disclosed in which the instruction control word is supplied using data bus as one operand and the data to be operated is supplied through another operand. Also disclosed is a method for the provision of operation-code along with data/operands using a short... Agent: Hahn And Moodley, LLP
20090031116 - Three operand instruction extension for x86 architecture: A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090031118 - Apparatus and method for controlling order of instruction: An apparatus includes an instruction generator which generates a load instruction and a first store instruction from a program, a processor which executes said load and store instruction, wherein said instruction generator analyzes a relevancy between said load instruction and said first store instruction with respect to memory addresses accessed... Agent: Mcginn Intellectual Property Law Group, Pllc
20090031119 - Method for the operation of a multiprocessor system in conjunction with a medical imaging system: The invention relates to a method for operating a multiprocessor system, especially in conjunction with a medical imaging system. The invention also relates to a medical imaging device which is designed to perform this method. The multiprocessor system in this case has at least two processing units, at least one... Agent: Siemens Corporation Intellectual Property Department
20090031121 - Apparatus and method for real-time microcode patch: An apparatus for performing microcode patches that is both fast and flexible. In one embodiment, an apparatus for performing a real-time microcode patch is provided. The apparatus includes a patch array and a mux. The patch array receives a microcode ROM address and determines that the microcode ROM address matches... Agent: Huffman Law Group, P.c.
20090031120 - Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system: One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instructions. A detector determines if an instruction is a high latency instruction... Agent: Mark P. Kahler01/22/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090024829 - Mixed torus and hypercube multi-rank tensor expansion method: The present invention provides a mixed torus and hypercube multi-rank tensor expansion method which can be applied to the communication subsystem of a parallel processing system. The said expansion method is based on the conventional torus and hypercube topologies. A mixed torus and hypercube multi-rank tensor expansion interconnection network is... Agent: William H. Honaker Dickinson Wright Pllc
20090024830 - Executing multiple instructions multiple data ('mimd') programs on a single instruction multiple data ('simd') machine: Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising... Agent: Ibm (roc-blf)
20090024831 - Executing multiple instructions multiple data ('mimd') programs on a single instruction multiple data ('simd') machine: Executing MIMD programs on a SIMD machine, including establishing on the SIMD machine a plurality of SIMD partitions; booting a first SIMD partition in MIMD mode; executing, on a compute node of the first SIMD partition booted in MIMD mode, a MIMD accelerator program; executing a SIMD program in a... Agent: Ibm (roc-blf)
20090024832 - Process for the automatic production of a processor from a machine description: The invention is based on the task to undertake machine descriptions, with which an automated optimal hardware design of SIMD processors can be carried out. This is solved by the fact that functional units are selected from a criterion in the machine description, which is vector processible. A first or... Agent: 24ip Law Group Usa, Pllc
20090024833 - Multiprocessor node controller circuit and method: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a... Agent: Baker Botts L.l.p.
20090024834 - Multiprocessor apparatus: Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor through a tightly coupled bus by the... Agent: Sughrue Mion, Pllc
20090024835 - Speculative memory prefetch: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090024836 - Multiple-core processor with hierarchical microcode store: A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090024838 - Mechanism for suppressing instruction replay in a processor: A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued.... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090024837 - System and method for language specification: Described are a system and method for language specification. The device may include (a) a processor running an operating system and (b) an image capturing device scanning an image. The operating system is configured to display a user interface. The image includes data that is transmitted to the operating system... Agent: Fay Kaplun & Marcin, LLP/ Motorola
20090024840 - Instruction code compression method and instruction fetch circuit: An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands and having the same number of bits... Agent: Volentine & Whitt Pllc
20090024839 - Variable instruction set microprocessor: The data operands of the said microprocessor can be with a variable length, independent of, and smaller or larger than the 8/16/32/64/128 bit data bus length of the general fixed instructions microprocessor. The speed of executing of the custom commands of the said can be the maximum internal speed of... Agent: Paul Arssov
20090024841 - Register file backup queue: A register file backup system for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090024842 - Precise counter hardware for microcode loops: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)01/15/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090019257 - Method and apparatus for length decoding and identifying boundaries of variable length instructions: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090019258 - Fault tolerant self-optimizing multi-processor system and method thereof: A fault-tolerant self-optimizing multi-processor system is disclosed that includes a plurality of redundant network switching units and a plurality of processors electrically coupled to the network switching units. Each processor comprises a local memory, local storage, multiple network interfaces and a routing agent (RA). The RAs form a unidirectional virtual... Agent: Volpe And Koenig, P.C.
20090019259 - Multiprocessing method and multiprocessor system: A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are... Agent: Arent Fox LLP
20090019261 - High-performance, superscalar-based computer system with out-of-order instruction execution: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units,... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090019260 - Mass prefetching method for disk array: Disclosed herein is a mass prefetching method for disk arrays. In order to improve disk read performance for a non-sequential with having spatial locality as well as a sequential read, when a host requests a block to be read, all the blocks of the strip to which the block belongs... Agent: H.c. Park & Associates, PLC
20090019262 - Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second... Agent: Texas Instruments Incorporated
20090019263 - Method and apparatus for length decoding variable length instructions: A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090019264 - Adaptive execution cycle control method for enhanced instruction throughput: A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is... Agent: Dillon & Yudell LLP
20090019265 - Adaptive execution frequency control method for enhanced instruction throughput: A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are scheduled to be executed. The logic/compiler then triggers the CPM unit to automatically switch... Agent: Dillon & Yudell LLP
20090019266 - Information processing apparatus and information processing system: With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090019267 - Method, system, and apparatus for dynamic reconfiguration of resources: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090019268 - Processor: The processor includes: a plurality of functional bocks that are respectively synchronized and operates to perform a process according to a control signal; a connection unit that is changeable to a smaller bandwidth than a bandwidth of inputs/outputs of the respective functional blocks and is connected between the respective functional... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090019269 - Methods and apparatus for a bit rake instruction: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any... Agent: Peter H. Priest
20090019270 - Embedded device program debug control: An embedded processor system includes an integrated development environment and an embedded processor system operating system. The operating system is operable to run on the embedded processor system, and a command queue is operable to receive commands from a debugging module external to the embedded processor system. A command queue... Agent: Schwegman, Lundberg & Woessner, P.A.
20090019271 - Information processing apparatus, information processing method, and storage medium: An information processing apparatus having a storage unit configured to execute a workflow with a plurality of processes combined therein and hold history information of the workflow, the information processing apparatus comprising an instructing unit configured to instruct such that a test workflow regarding a workflow selected to be executed... Agent: Canon U.s.a. Inc. Intellectual Property Division
20090019272 - Store queue architecture for a processor that supports speculative execution: Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20090019273 - Exception-based error handling in an array-based language: A computer-readable medium stores computer-executable instructions. The medium may hold: one or more instructions for executing a first code block; one or more instructions for generating an exception object based on the executing of the first code block; one or more instructions for receiving the exception object at a second... Agent: Venable LLP01/08/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090013152 - Computing unit and image filtering device: A processor capable of performing a filter processing in a high speed is provided. A computing unit comprises a computer for performing a filter processing. Data supply to the computer is performed by an internal register configured by a flip-flop. Data read from the internal register is outputted to a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20090013150 - Simd microprocessor and data transfer method for use in simd microprocessor: A disclosed SIMD microprocessor includes plural processor elements each having n arithmetic circuits and n registers configured to temporarily store data pieces to be input to the arithmetic circuits, n being a natural number equal to or greater than 2, and; a control circuit configured to determine an arrangement order... Agent: Dickstein Shapiro LLP
20090013151 - Simd type microprocessor: An SIMD type microprocessor is disclosed. The SIMD type microprocessor includes plural PEs (processor elements) each of which provides an ALU (arithmetic and logic unit) for lower-order bits, an ALU for upper-order bits, a control circuit for lower-order bits, a control circuit for upper-order bits, a range determining circuit for... Agent: Dickstein Shapiro LLP
20090013153 - Processor exclusivity in a partitioned system: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control... Agent: David E. Lovejoy, Reg. No. 22,748
20090013154 - Multilayer distributed processing system: The independencies of a plurality of layers executing dividingly a transaction can be easily enhanced. Anode (30) assigns to a transaction to anode (30) of a lower layer through a distributed transaction management section. The node (30) shares a predetermined transaction with the node (30) of the lower layer along... Agent: Hewlett Packard Company
20090013155 - System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090013157 - Management of software implemented services in processor-based devices: A service management system for devices with embedded processor systems manages use of memory by programs implementing the services by assigning services to classes and limiting the number of services per class that can be loaded into memory. Classes enable achieving predictable and stable system behavior, defining the services and... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20090013156 - Processor communication tokens: The invention provides a method of transmitting messages over an interconnect between processors, each message comprising a header token specifying a destination processor and at least one of a data token and a control token. The method comprises: executing a first instruction on a first one of the processors to... Agent: Sughrue Mion, PLLC
20090013159 - Queue processor and data processing method by the queue processor: The queue processor equips multiple operation data storing queues (18, 19) for storing the obtained memory stored data and intermediate result data during processing, and multiple execution units (17a, 17b, 17c) accessible to each of multiple operation data storing queues (18, 19), the execution unit (17a, 17b, 17c) doing the... Agent: Ndq&m Watchstone LLP
20090013158 - System and method for assigning tags to control instruction processing in a superscalar processor: A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for tagging instructions. A register file stores information required... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090013160 - Dynamically composing processor cores to form logical processors: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected,... Agent: Winstead PC
20090013161 - Processor for making more efficient use of idling components and program conversion apparatus for the same: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by... Agent: Snell & Wilmer L.L.P. (panasonic)01/01/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090006808 - Ultrascalable petaflop parallel supercomputer: A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006809 - Non-disruptive code update of a single processor in a multi-processor computing system: Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor... Agent: Law Firm Of Dan Shifrin
20090006810 - Mechanism to support generic collective communication across a variety of programming models: A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation an executor that executes the task, a multisend module to perform one or more data... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006812 - Method and apparatus for accessing a cache with an effective address: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090006811 - Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction: A method of expanding a conditional instruction having a plurality of operands within a pipeline processor is disclosed. The method identifies the conditional instruction prior to an issue stage and determines if the plurality of operands exceeds a predetermined threshold. The method expands the conditional instruction into a non-conditional instruction... Agent: Qualcomm Incorporated
20090006813 - Data forwarding from system memory-side prefetcher: An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a system memory-side prefetcher that is coupled to a memory controller. The system memory-side prefetcher includes a stride detection unit to identify one or more patterns in a stream. The system memory-side prefetcher also includes a prefetch... Agent: Intel Corporation C/o Intellevate, LLC
20090006814 - Immediate and displacement extraction and decode mechanism: An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit and at least one constant steer network. During operation, the instruction decode unit... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090006815 - System and method for interfacing devices: A system in one embodiment includes (i) an interface module to control and monitor the system; a plurality of power cells which act as a point of power delivery and monitor environmental variables that effect function and reliability, (ii) a radio frequency transmitter and receiver to manage nodes distributed across... Agent: Bell, Boyd & Lloyd, LLP
20090006816 - Inter-cluster communication network and heirarchical register files for clustered vliw processors: A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue... Agent: Texas Instruments Incorporated
20090006817 - Mechanisms for placing a processor into a gradual slow mode of operation: Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090006818 - Method and apparatus for multiple load instruction execution: A method and apparatus for executing instructions. The method includes receiving a first load instruction and a second load instruction. The method also includes issuing the first load instruction and the second load instruction to a cascaded delayed execution pipeline unit having at least a first execution pipeline and a... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090006820 - issue unit for placing a processor into a gradual slow mode of operation: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090006819 - Single hot forward interconnect scheme for delayed execution pipelines: A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline.... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090006821 - Apparatus, method, and computer program product for processing information by controlling arithmetic mode: An HW arithmetic unit executes a predetermined arithmetic operation. An arithmetic-mode determining unit determines, based on an attribute or a content of data relating to processing that has requested the arithmetic operation, either a synchronous mode that executes the processing after waiting for completion of the arithmetic operation by an... Agent: Amin, Turocy & Calvin, LLP
20090006822 - Device and method for adding and subtracting two variables and a constant: A method device and a method. The method includes fetching an instruction, decoding an instruction that includes an instruction type field, a first variable field, a second variable field, a result field and a constant field; selecting an operation out of addition operation, a subtraction operation and another type of... Agent: Freescale Semiconductor, Inc. Law Department
20090006823 - Design structure for single hot forward interconnect scheme for delayed execution pipelines: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090006824 - Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling: A design structure for a circuit function that implements a load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first... Agent: Dillon & Yudell LLP
20090006825 - Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090006826 - Branch prediction methods and devices capable of predicting first taken branch instruction within plurality of fetched instructions: A branch prediction method, capable of predicting a first taken branch instruction within a plurality of fetched instructions, includes: determining whether one of the fetched instructions is the first taken branch instruction to be predicted according to hint instruction(s) or according to latest statistics of whether respective fetched instructions have... Agent: North America Intellectual Property CorporationPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150521:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.