Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 12/08

20080320272 - Partition priority controlling system and method: A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one... Agent: Staas & Halsey LLP

20080320273 - Interconnections in simd processor architectures: A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 . . . 14N), each memory portion being assigned to a particular processing element.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080320274 - Age matrix for queue dispatch order: An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of... Agent: Zilka-kotab, PC- Rmi

20080320275 - Concurrent exception handling: Various technologies and techniques are disclosed for providing concurrent exception handling. Exceptions that occur in concurrent workers are caught. The caught exceptions are then forwarded from the concurrent workers to a coordination worker. The caught exceptions are finally aggregated into an aggregation structure, such as an aggregate exception object. This... Agent: Microsoft Corporation

20080320276 - Digital computing device with parallel processing: A digital processing device comprising a plurality of parallel processing units each coupled in parallel with one another. Each of the plurality of parallel processing units comprises at least one data memory storage unit; at least one input register coupled to the at least one data memory storage unit; and... Agent: Schneck & Schneck

20080320277 - Thread optimized multiprocessor architecture: In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein... Agent: Morgan Lewis & Bockius LLP

20080320279 - Management of a communication link extended to one or more slave devices: A master device for managing a communications link to slave devices (for example in the context of a Wireless USB cluster), wherein the master device is configured to facilitate avoidance of unnecessary waking of the slave devices.... Agent: Fitzpatrick Cella Harper & Scinto

20080320278 - System and method for efficient data transmission in a multi-processor environment: A system and method which provides for efficient data transmission between multiple microprocessors in a computer system is disclosed. A physical data path is divided into one or more data queues which may be virtual connection queues. The virtual connection queues are configured to adaptively split or merge based on... Agent: Knobbe, Martens, Olson, & Bear, LLP

20080320280 - Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically comprises... Agent: Young & Thompson

20080320281 - Processing module with mmw transceiver interconnection: A processing module includes a fetch and decode module, an instruction register, a data register, an execution module, and a MMW transceiver section. The fetch and decode module is operable to fetch and decode an instruction of a program and to identify data associated with the instruction. The execution module... Agent: Garlick Harrison & Markison

20080320282 - Method and systems for providing transaction support for executable program components: Methods and systems are described for providing transaction support for executable program components. In one embodiment, transaction information is associated with an instruction included in an executable addressable entity included in an executable program component generated from source code written in a programming language, wherein the transaction information is independent... Agent: Scenera Research, LLC

20080320283 - Method and systems for providing transaction support for executable program components: A data processing circuit has a programmable processor (12a, b) with an instruction set that comprises an new type of instruction. This instruction has a first operand that refers to a string of bits, and a second operand that refers to a position in that string of bits. The programmable... Agent: Philips Intellectual Property & Standards

20080320284 - Virtual serial-stream processor: A virtual serial-stream processor or system consists of one or more data input ports, zero or more data output ports, zero or more virtual control ports, one or more virtual serial and stream processing cores, one or more virtual serial control processors, and memory. Virtual components are spread across multiple... Agent: Lowrie, Lando & Anastasi, LLP

20080320285 - Distributed digital signal processor: A distributed digital signal processor (DSP) includes instruction memory, data memory, a multiply-accumulate module, an instruction MMW transceiver, a data MMW transceiver, and a multiply-accumulate transceiver. The multiply-accumulate module performs a function upon first and second data elements in accordance with a command of an instruction. The instruction MMW transceiver... Agent: Garlick Harrison & Markison

20080320286 - Dynamic object-level code translation for improved performance of a computer processor: A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic... Agent: Connolly Bove Lodge & Hutz LLP (ibm Microelectronics Division)

20080320287 - Method and device for performing switchover operations in a computer system having at least two processing units: A method and device for performing switchover operations in a computer system having at least two processing units, a switchover device, and a comparison device, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating... Agent: Kenyon & Kenyon LLP

20080320288 - Branch prediction apparatus of computer: One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch... Agent: Staas & Halsey LLP

20080320289 - Storage medium storing calculation processing visualization program, calculation processing visualization apparatus, and calculation processing visualization method: The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the... Agent: Greer, Burns & Crain

20080320291 - Concurrent exception handling: Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled... Agent: Microsoft Corporation

20080320290 - Exception-based timer control: A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in response to the exception and based on a characteristic of the exception. A method... Agent: Larson Newman Abel Polansky & White, LLP

20080313421 - Low power-consumption data processor: A low power-consumption data processor, wherein instruction decoding is performed on an instruction memory and an instruction register by an instruction decoding unit through an instruction bus, being characterized in that an instruction decoding circuit is disposed between the instruction register, a program counter and an arithmetic logic unit, wherein... Agent: Wpat, PC

20080313422 - Enhanced single threaded execution in a simultaneous multithreaded microprocessor: A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080313423 - Distributed memory type information processing system: An information processing system includes a plurality of PMM and data transmission paths for connection between the PMM and transmitting a value of a PMM to another PMM. A memory of each PMM holds a list of values of first items arranged in the ascending order or descending order without... Agent: Griffin & Szipl, PC

20080313425 - Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor: A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency miss, the processing unit enters a load lookahead mode. Responsive... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080313424 - Method and apparatus for spatial register partitioning with a multi-bit cell register file: There is provided a multi-bit storage cell for a register file. The storage cell includes a first set of storage elements for a vector slice. Each storage element respectively corresponds to a particular one of a plurality of thread sets for the vector slice. The storage cell includes a second... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080313427 - Directory-based data transfer protocol for multiprocessor system: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20080313426 - Information processing apparatus and information processing method: An asynchronous communicating part executes an asynchronous communication between a first device and a second device. A first process executing part executes a processing in the first device by use of the asynchronous communication as a trigger. A second process executing part executes a processing in the second device by... Agent: Edwards Angell Palmer & Dodge LLP

20080313428 - Microprocessor: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied... Agent: Milde & Hoffberg, LLP

20080313429 - Information processing apparatus: When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction “GETACX Dm,Dn” performs saving of necessary data from all registers. “Dm” is a value output from a general register group 104 to a first data input bus 120.... Agent: Mcdermott Will & Emery LLP

20080313430 - Method and system for increasing quantum computer processing speed using digital co-processor: A computer system includes a quantum computer, a classical co-processor and an interface that transmits at least part of at least one problem between the quantum computer and the classical co-processor. A digital computer may be coupled to the quantum computer and classical co-processor. Problems may be decomposed for solution... Agent: Seed Intellectual Property Law Group PLLC

20080313431 - Method and system for altering processor execution of a group of instructions: An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instructions. An instruction register receives the group of... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080313432 - Block allocation times in a computer system: A method and apparatus improves the block allocation time in a parallel computer system. A pre-load controller pre-loads blocks of hardware in a supercomputer cluster in anticipation of demand from a user application. In the preferred embodiments the pre-load controller determines when to pre-load the compute nodes and the block... Agent: Martin & Associates, LLC

20080313433 - Processor for simultaneously executing multiple conditional execution instruction groups: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing... Agent: Hitt Gaines P.C.

20080313434 - Rendering processing apparatus, parallel processing apparatus, and exclusive control method: A DDA 34 notifies the coordinates of a rasterized pixel to an exclusive control part 40, acquires a unique identification number associated with the pixel position from the exclusive control part 40, and adds the identification number to pixel data and supplies it to a shader 20. A plurality of... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080313435 - Data processing apparatus and method for executing complex instructions: A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data processing apparatus, those instructions including at least one complex instruction defining a sequence of operations to be performed. The data processing apparatus comprises a... Agent: Nixon & Vanderhye, PC

20080313436 - Handling of extra contexts for shader constants: The present invention provides a system for handling extra contexts for shader constants, and applications thereof. In an embodiment there is provided a computer-based method for executing a series of compute packets in an execution pipeline. The execution pipeline includes a first plurality of registers configured to store state-updates of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080313437 - Method and apparatus for employing multi-bit register file cells and smt thread groups: There are provided methods and apparatus for multi-bit cell and SMT thread groups. An apparatus for a register file includes a plurality of multi-bit storage cells for storing a plurality of bits respectively corresponding to a plurality of threads. The apparatus further includes a plurality of port groups, operatively coupled... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080313438 - Unified cascaded delayed execution pipeline for fixed and floating point instructions: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080313441 - Method and structure for producing high performance linear algebra routines using register block data format routines: A method (and structure) of executing a matrix operation, includes, for a matrix A, separating the matrix A into blocks, each block having a size p-by-q. The blocks of size p-by-q are then stored in a cache or memory in at least one of the two following ways. The elements... Agent: Mcginn Intellectual Property Law Group, PLLC

20080313439 - Pipeline device with a plurality of pipelined processing units: In a pipeline device, the output of each of processing units is connected to a corresponding one of data output lines of data transfer lines. Input selectors are provided for the processing units, respectively. Each input selector selects one of the data transfer lines except for one data output line... Agent: Posz Law Group, PLC

20080313440 - Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080313442 - Debugging techniques for a programmable integrated circuit: Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit... Agent: Qualcomm Incorporated

20080313444 - Microcomputer and dividing circuit: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080313443 - Processor apparatus: There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or each of a plural number of conditions, and for performing branching to a branch... Agent: Sughrue Mion, PLLC

20080313445 - Method and system for preventing livelock due to competing updates of prediction information: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is... Agent: Duke W. Yee

20080313446 - Processor predicting branch from compressed address information: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting... Agent: Staas & Halsey LLP

20080307193 - Semiconductor integrated circuit: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m≧2) and less than the total number of m bits as an instruction that carries... Agent: Mcginn Intellectual Property Law Group, PLLC

20080307194 - Parallel, low-latency method for high-performance deterministic element extraction from distributed arrays: The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a local array with elements from input, a module that submits a largest element value in the local array and a processor ID for... Agent: Cantor Colburn LLP - IBM Rochester Division

20080307195 - Parallel, low-latency method for high-performance speculative element extraction from distributed arrays: The present invention provides a system and method for extracting elements from distributed arrays on a parallel processing system. The system includes a module that populates a result array with globally largest elements from the input, a module that generates a partition element, a module that counts the number of... Agent: Cantor Colburn LLP - IBM Rochester Division

20080307196 - Integrated processor array, instruction sequencer and i/o controller: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines... Agent: Dla Piper US LLP

20080307197 - System and method for persistent hardware system serial numbers: A system for computer hardware serial number management includes a computer system chassis comprising a chassis serial number. The chassis serial number is embodied on the computer system chassis as a physical serial number. A first RFID tag is attached to the computer system chassis at a first location. The... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.

20080307198 - Signal-processing apparatus and electronic apparatus using same: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount... Agent: Wenderoth, Lind & Ponack L.L.P.

20080307200 - Method of burning in extended display identification data without using a computer: The present invention relates to a method of burning in extended display identification data (EDID) without using a computer, wherein an EDID burning device is connected to an input device via an input device interface, a product barcode labeled on a to-be-burned display device is inputted for obtaining product data... Agent: Bacon & Thomas, PLLC

20080307199 - Portable extended display identification data burning device: The present invention relates to a portable extended display identification data (EDID) burning device, which could perform an EDID burning operation via an input device without connecting to a computer. The portable EDID burning device comprises: at least one video connection interface connected to a to-be-burned display device, a memory... Agent: Bacon & Thomas, PLLC

20080307201 - Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file: A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the... Agent: Mark P. Kahler

20080307202 - Loading test data into execution units in a graphics card to test the execution units: Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20080307204 - Fast static rotator/shifter with non two's complemented decode and fast mask generation: In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. Coupled to receive the input operand and the shift count, the rotator is configured to rotate the... Agent: Mhkkg, PC/apple, Inc.

20080307203 - Scaling instruction intervals to identify collection points for representative instruction traces: A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080307205 - Computationally efficient mathematical engine: A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic unit circuits that are configured to process data in parallel to... Agent: Volpe And Koenig, P.C. Dept. Icc

20080307206 - Method and apparatus to efficiently evaluate monotonicity: A method and processor to evaluate a monotonicity of a set of input values is disclosed. The processor achieves high processing power by means of an arbitrary number of identical parallel processing elements. Each processing element allows instruction dependent data paths and makes use of ALU factories which consist of... Agent: Schneck & Schneck

20080307207 - Data exchange and communication between execution units in a parallel processor: A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more... Agent: Shemwell Mahamedi LLP

20080307208 - Application specific processor having multiple contexts: An application specific processor executes multiple dedicated applications in a system having a main control processor for controlling the operation of the system. The application specific processor includes a first context for executing a corresponding first application and a second context for executing a corresponding second application. An instruction memory... Agent: Greer, Burns & Crain

20080307209 - Methods and apparatus for implementing polymorphic branch predictors: A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to select one or more of the branch prediction methods in accordance with a dynamic setting to optimize performance of the branch predictor... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080307210 - System and method for optimizing branch logic for handling hard to predict indirect branches: A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080301401 - Processor: A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit... Agent: SocalIPLaw Group LLP

20080301402 - Method and system for stealing interrupt vectors: A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080301403 - System for integrity protection for standard 2n-bit multiple sized memory devices: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more... Agent: Lsi Corporation

20080301404 - Method for controlling an electronic circuit and controlling circuit: A method for controlling an electronic circuit including selecting at least one pre-stored generating rule from a plurality of pre-stored generating rules according to which a message which is to be transmitted to the electronic circuit for carrying out a controlling function to control the electronic circuit is to be... Agent: Dickstein Shapiro LLP

20080301405 - System and method for automatically segmenting and populating a distributed computing problem: The initial partitioning of a distributed computing problem can be critical, and is often a source of tedium for the user. A method is provided that automatically segments the problem into fixed sized collections of original program cells (OPCs) based on the complexity of the problem specified, and the combination... Agent: Cantor Colburn, LLP - IBM Arc Division

20080301406 - System and method for allocating communications to processors in a multiprocessor system: In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific 5 processor without using a locking mechanism specific to the resources required for assignment.... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20080301407 - Resolving a layer 3 address in a processor system with a unified ip presence: Resolving a Layer 3 address includes maintaining an address resolution table at each slave processor of a number of slave processors. The slave processors have a master processor, and the master processor and the slave processors are associated with a unified address. An address resolution table includes one or more... Agent: Baker Botts L.L.P.

20080301408 - System comprising a plurality of processors and method of operating the same: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by... Agent: Williams, Morgan & Amerson

20080301409 - Scheduling threads in a processor: The invention provides a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of those instructions defining a memory access operation. The processor comprises: a plurality of instruction buffers, each for holding at least one instruction of a thread associated... Agent: Sughrue Mion, PLLC

20080301410 - Processor configured for operation with multiple operation codes per instruction: A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a... Agent: Ryan, Mason & Lewis, LLP

20080301411 - Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted... Agent: Ibm Corporation (jvm)

20080301412 - High speed multiplexer: According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate... Agent: Farjami & Farjami LLP

20080301413 - Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing: A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and... Agent: Rines & Rines

20080301414 - Efficient complex multiplication and fast fourier transform (fft) implementation on the manarray architecture: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations... Agent: Peter H. Priest

20080301415 - Information processing system: An information processing system includes a first processor that accesses a first memory, a second processor that accesses a second memory, and a data transfer unit for executing data transfer between the first memory and the second memory. The first processor executes functions of translating an instruction out of instructions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080301416 - System and program product of doing pack unicode z series instructions: Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080301417 - System and method for debugging of computer: A method of returning to a state in the history of execution of a computer program, said state comprising a set of values of one or more of registers of a processor on which the program is running, working memory space to which the program has access and operating system... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20080301418 - Tracing command execution in a parallel processing system: Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one... Agent: Shemwell Mahamedi LLP

20080301419 - Process model control flow with multiple synchronizations: Activations of a plurality of incoming branches may be detected at a synchronization point having a plurality of outgoing branches. A first synchronization may be executed after a first number of activations is detected, and at least one of a plurality of outgoing branches from the synchronization point may be... Agent: Brake Hughes Bellermann LLP

20080301420 - Branch prediction control device having return address stack and method of branch prediction: A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address... Agent: Mcginn Intellectual Property Law Group, PLLC

20080301421 - Method of speeding up execution of repeatable commands and microcontroller able to speed up execution of repeatable commands: A method to speed up the execution of repeatable commands and a microcontroller able to speed up the execution of repeatable commands are disclosed. When the microcontroller is to execute repeatable commands in a program, it temporarily stores repeatable commands to a storage unit. If the execution of the repeatable... Agent: Rosenberg, Klein & Lee