Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 11/08

20080294870 - Switch memory architectures: The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE), (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between two adjacent processes by passing a memory handle and the status registers (memory control information)... Agent: Lathrop & Gage Lc

20080294871 - Multidimensional processor architecture: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able... Agent: Hogan & Hartson LLP

20080294872 - Defragmenting blocks in a clustered or distributed computing system: Embodiments of the invention provides techniques for defragmenting blocks of resources allocated to perform computing jobs on a distributed or clustered system so that more contiguous physical resources may be made available to users submitting new job requests. Typically, the defragmentation process is performed when a job is submitted that... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080294874 - Allocation of combined or separate data and control planes: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.... Agent: Lemoine Patent Services, PLLC

20080294873 - Microcomputer: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values... Agent: Alan R. Loudermilk

20080294875 - Parallel processor for efficient processing of mobile multimedia: Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point... Agent: Ladas & Parry LLP

20080294876 - Control device with flag registers for synchronization of communications between cores: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080294877 - Numerical controller having function of resuming look-ahead of block: A numerical controller which performs look-ahead control by suspending analysis of a read block of a machining program and resuming the analysis of the read block at a suspended stage when execution of a block immediately preceding the read block is completed. The numerical controller successively reads and analyzes blocks... Agent: Drinker Biddle & Reath (dc)

20080294878 - Processor system and exception processing method: When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080294879 - Asynchronous ripple pipeline: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080294880 - Customization of a microprocessor and data protection method: An electronic circuit containing a processing unit for executing program instructions, including at least one unit for recognizing at least one first instruction operator in the program and for converting this first operator into another instruction operator, both operators being interpretable by the processing unit. A method for controlling the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080294881 - Method and apparatus for instruction completion stall identification in an information handling system: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software... Agent: Mark P. Kahler

20080294882 - Distributed loop controller architecture for multi-threading in uni-threaded processors: In one aspect, a virtually multi-threaded distributed instruction memory hierarchy that can support the execution of multiple incompatible loops in parallel is disclosed. In addition to regular loops, irregular loops with conditional constructs and nested loops can be mapped. The loop buffers are clustered, each loop buffer having its own... Agent: Knobbe Martens Olson & Bear LLP

20080294883 - Mock exceptions in a host add-in environment: Mock exceptions, including mock exception types, are defined by a host to be raised in a plug-in. The mock exceptions might be sanitized. They might be transported from the plug-in to the host. Mock exceptions might also be mapped to real exceptions, which are raised in the host and handled... Agent: Microsoft Corporation

20080294885 - Method to detect a stalled instruction stream and serialize micro-operation execution: A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080294884 - Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors: A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080288745 - Generating predicate values during vector processing: A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP

20080288748 - Dynamic core switching: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second... Agent: Harness, Dickey & Pierce P.L.C

20080288746 - Executing multiple instructions multiple data ('mimd') programs on a single instruction multiple data ('simd') machine: Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous... Agent: Ibm (roc-blf)

20080288747 - Executing multiple instructions multiple data ('mimd') programs on a single instruction multiple data ('simd') machine: Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program by an operating system on a compute node in... Agent: Ibm (roc-blf)

20080288749 - Read-copy update grace period detection without atomic instructions that gracefully handles large numbers of processors: A method, system and computer program product for avoiding unnecessary grace period token processing while detecting a grace period without atomic instructions in a read-copy update subsystem or other processing environment that requires deferring removal of a shared data element until pre-existing references to the data element are removed. Detection... Agent: Walter W. Duft

20080288750 - Small barrier with local spinning: A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object... Agent: Microsoft Corporation

20080288751 - Technique for prefetching data based on a stride pattern: A processor system (100) includes a central processing unit (102) and a prefetch engine (110). The prefetch engine (110) is coupled to the central processing unit (102). The prefetch engine (110) is configured to detect, when data associated with the central processing unit (102) is read from a memory (114),... Agent: Larson Newman Abel Polansky & White, LLP

20080288752 - Design structure for forwarding store data to loads in a pipelined processor: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080288753 - Methods and apparatus for emulating the branch prediction behavior of an explicit subroutine call: An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related... Agent: Qualcomm Incorporated

20080288754 - Generating stop indicators during vector processing: A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP

20080288755 - Clock driven dynamic datapath chaining: A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the... Agent: Stolowitz Ford Cowger, LLP/cypress

20080288756 - \"or\" bit matrix multiply vector instruction: A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system.... Agent: Schwegman, Lundberg & Woessner, P.A.

20080288757 - Communicating instructions and data between a processor and external devices: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080288758 - Method and device for switching over in a computer system having at least two execution units: A method and device for switching over in a computer system having at least two execution units, switching being carried out between at least two operating modes, and the operating modes corresponding to states of the computer system, a first state corresponding to a comparison mode and a second state... Agent: Kenyon & Kenyon LLP

20080288759 - Memory-hazard detection and avoidance instructions for vector processing: A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical memory hazards between memory addresses if memory operations... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP

20080288760 - Branch target prediction for multi-target branches by identifying a repeated pattern: An information processing system for branch target prediction includes: a first memory for storing entries for multi-target branch, wherein each entry includes a plurality of target addresses representing a history of target addresses for each single branch in the multi-target branch, and wherein said first memory stores an entry for... Agent: Michael Buchenhorner, P.A.

20080288761 - Method and system for efficient tentative tracing of software in multiprocessors: A method of tentative tracing execution events in a multiprocessor system. Each processor stores tentative events in a corresponding buffer. The processor sets pointers in an array to a head and tail of a thread. When a condition triggers a tentative thread to be committed, the processor marks the first... Agent: Dillon & Yudell LLP

20080282058 - Message queuing system for parallel integrated circuit architecture and related method of operation: An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the VPEs and the external memory. Each VPE contains a plurality of data processing units and a message queuing system adapted to... Agent: Patterson & Sheridan, L.L.P.

20080282059 - Method and apparatus for determining membership in a set of items in a computer system: A method and apparatus for maintaining membership in a set of items to be used in a predetermined manner in a computer system. A representation of each member of the set is mapped into a number of components of a primary and secondary vector when a member is added to... Agent: Ibm Corporation, T.j. Watson Research Center

20080282060 - Active memory command engine and method: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine,... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080282061 - Array type operation device: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an... Agent: Snell & Wilmer L.L.P. (matsushita)

20080282062 - Method and apparatus for loading data and instructions into a computer: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC

20080282063 - Methods and apparatus for latency control in a multiprocessor system: Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080282064 - System and method for speculative thread assist in a heterogeneous processing environment: A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080282065 - Image forming apparatus and control method for the same: An image forming apparatus includes a job-history managing unit that creates and manages a job history, registers a job history, as a job history instance, containing an operation code that instructs a series of job operations to be executed and also containing an operating condition of the job operation, and... Agent: Harness, Dickey & Pierce, P.L.C

20080282066 - Compact instruction set encoding: The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to... Agent: Sughrue Mion, PLLC

20080282067 - Issue policy control within a multi-threaded in-order superscalar processor: A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30,... Agent: Nixon & Vanderhye P.C.

20080282068 - Host command execution acceleration method and system: The present invention sets forth an interface method and system for host acceleration between an electronic device and a host PC. The system comprises an acceleration unit for rapidly classifying a type of an host command then issuing a flag signal to a microprocessor. The microprocessor then executes corresponding actions... Agent: Madson & Austin

20080282069 - Method and system for designing a flexible hardware state machine: Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered;... Agent: Klein, O'neill & Singh, LLP

20080282070 - Simd arithmetic device capable of high-speed computing: A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or in a combination of these units. A data select circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080282071 - Microprocessor and register saving method: A microprocessor which realizes fast register saving and restoring which are involved in subroutine calls, and is capable of reducing the scale of a program. A register file is provided with at least one register for storing data to be used for computational processing. A saving memory stores therein data... Agent: Staas & Halsey LLP

20080282072 - Executing software within real-time hardware constraints using functionally programmable branch table: A computer system is disclosed which includes a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080282073 - Comparing text strings: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer... Agent: Trop Pruner & Hu, PC

20080276068 - Ims network architecture with integrated network elements: An IP multimedia subsystem (IMS) network includes (i) a plurality of network elements that are directly or indirectly interconnected for carrying out communications and (ii) an integrated IMS network control unit interfaced with the other network elements. The control unit integrates three IMS network functions into one network node: a... Agent: Mccormick, Paulding & Huber LLP

20080276069 - Method and apparatus for predictive decoding: Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor information for the fetched instruction from the predictor; and generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction. The decode operation stream... Agent: Cantor Colburn LLP-ibm Burlington

20080276070 - Reducing the fetch time of target instructions of a predicted taken branch instruction: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC

20080276071 - Reducing the fetch time of target instructions of a predicted taken branch instruction: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC

20080276072 - System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor: A method of executing a conditional instruction within a pipeline processor having a plurality of pipelines, the processor having a first condition code register associated with a first pipeline and a second condition code register associated with a second pipeline is disclosed. The method saves a most recent condition code... Agent: Qualcomm Incorporated

20080276073 - Apparatus for and method of distributing instructions: An apparatus is provided for buffering instructions. An instruction store has memory locations for storing instructions. Each instruction can be associated with a timer such that an instruction dispatcher causes the instruction to be sent when the timer indicates that the instruction should be sent.... Agent: Fish & Richardson PC

20080276074 - Simple load and store disambiguation and scheduling at predecode: Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080276075 - Simple load and store disambiguation and scheduling at predecode: Embodiments of the invention provide a method and processor for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction to be executed in the processor and detecting a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080276076 - Method and apparatus for register renaming: A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080276077 - Method to reduce the number of load instructions searched by stores and snoops in an out-of-order processor: A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the... Agent: Cantor Colburn LLP-ibm Yorktown

20080276078 - Method and apparatus for context address generation for motion vectors and coefficients: A method for high/low usage is provided. The method receives a macroblock data structure and a syntax element at a digital signal processing engine. Further, the method classifies the syntax element as high use or low use. In addition, the method sends the syntax element from the digital signal processing... Agent: Motorola, Inc. Law Department

20080276079 - Mechanism to minimize unscheduled d-cache miss pipeline stalls: A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080276080 - Methods for storing branch information in an address table of a processor: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC

20080276081 - Compact representation of instruction execution path history: A method of representing instruction execution path history is provided. The method in one aspect may include gathering information associated with a current instruction, the information including at least a target address. Previously computed bits representing execution path history is modified and hashed based on the target address, to compute... Agent: Scully, Scott, Murphy & Presser, P.C.