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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) October patent listing 10/08

20080263317 - Datapipe destination and source devices: An integrated circuit (102) in communication with a host circuit (104) includes an interconnect bus (344) and a plurality of programmable elements (116-130). Each of the programmable elements (116-130) includes a control interface (354) for receiving a control signal, the control signal causing the memory element (338) to selectively operate... Agent: Hovey Williams LLP

20080263318 - Timed ports: A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time... Agent: Sughrue Mion, PLLC

20080263319 - Universal digital block with integrated arithmetic logic unit: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263320 - Executing a scatter operation on a parallel computer: Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an operational group of compute nodes and for storing contents scattered to that ranked node; and repeatedly for each position... Agent: Ibm (roc-blf)

20080263321 - Universal register rename mechanism for targets of different instruction types in a microprocessor: A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080263322 - Mac architecture for pipelined accumulations: A programmable accumulation module (324) with an embedded register array comprises a crosspoint switch (318), a control interface for receiving a control signal (359), a register array circuit (352), a multiplier module (348) for receiving two input values from the crosspoint switch (318) and multiplying the values, and an adder... Agent: Hovey Williams LLP

20080263323 - Reconfigurable computing architectures: dynamic and steering vector methods: A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution... Agent: Dunlap Codding, P.C.

20080263324 - Dynamic core switching: A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when... Agent: Harness, Dickey & Pierce P.L.C

20080263325 - System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor: A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection... Agent: Cantor Colburn LLP-ibm Yorktown

20080263326 - Method and apparatus for an efficient multi-path trace cache design: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.... Agent: Ference & Associates LLC

20080263327 - Automatically selecting firmware instructions for an operating system: Embodiments of the present invention pertain to automatically selecting firmware instructions for an operating system. According to one embodiment, at least a part of a first subset of firmware instructions on a computer system is executed. An automatic determination of whether the first subset of firmware instructions supports an operating... Agent: Hewlett Packard Company

20080263328 - Orthogonal register access: Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263329 - Parallel-prefix broadcast for a parallel-prefix operation on a parallel computer: A parallel-prefix broadcast for a parallel-prefix operation on a parallel computer includes: configuring, on each node, a parallel-prefix contribution buffer for storing the node's parallel-prefix contribution; configuring, on each node, a parallel-prefix results buffer for storing results of a operation, the results buffer having a position for each node that... Agent: Ibm (roc-blf)

20080263330 - Clocked ports: A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port... Agent: Sughrue Mion, PLLC

20080263331 - Universal register rename mechanism for instructions with multiple targets in a microprocessor: A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080263332 - Data processing apparatus and method for accelerating execution subgraphs: A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The... Agent: Nixon & Vanderhye, PC

20080263333 - Document processing method: The present invention discloses a method for processing document data to achieve document interoperation, and the method comprises: by an application, performing an operation on abstract unstructured information by issuing instruction(s) to a platform software; and by the said platform software, receiving the said instruction and performing the operation on... Agent: Ladas & Parry

20080263334 - Dynamically configurable and re-configurable data path: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263336 - Processor having efficient function estimate instructions: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080263335 - Representation of modal intervals within a computer: A modal interval representation having improved computational utility is provided. The modal interval representation generally includes a binary quantifier, and a set theoretical interval for select permutations of marks of a pair of marks of an IEEE standard 754 digital scale. The set theoretical interval includes combinations of real numbers,... Agent: Nawrocki, Rooney & Sivertson Suite 401, Broadway Place East

20080263337 - Instructions for ordering execution in pipelined processes: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution... Agent: Lieberman & Brandsdorfer, LLC

20080263338 - Exception operation apparatus, method and computer program for controlling debugging apparatus, and television and cellular phone providing the same: In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a break point is not set beforehand, a computer, which executes a program to be debugged,... Agent: Birch Stewart Kolasch & Birch

20080263339 - Method and apparatus for context switching and synchronization: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080263340 - Method and device for analyzing a signal from a computer system having at least two execution units: A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to... Agent: Kenyon & Kenyon LLP

20080263341 - Data processing apparatus and method for generating prediction data: A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction... Agent: Nixon & Vanderhye, PC

20080263342 - Apparatus and method for handling exception signals in a computing system: Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and... Agent: Wilmerhale/boston

20080263317 - Datapipe destination and source devices: An integrated circuit (102) in communication with a host circuit (104) includes an interconnect bus (344) and a plurality of programmable elements (116-130). Each of the programmable elements (116-130) includes a control interface (354) for receiving a control signal, the control signal causing the memory element (338) to selectively operate... Agent: Hovey Williams LLP

20080263318 - Timed ports: A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time... Agent: Sughrue Mion, PLLC

20080263319 - Universal digital block with integrated arithmetic logic unit: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263320 - Executing a scatter operation on a parallel computer: Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an operational group of compute nodes and for storing contents scattered to that ranked node; and repeatedly for each position... Agent: Ibm (roc-blf)

20080263321 - Universal register rename mechanism for targets of different instruction types in a microprocessor: A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080263322 - Mac architecture for pipelined accumulations: A programmable accumulation module (324) with an embedded register array comprises a crosspoint switch (318), a control interface for receiving a control signal (359), a register array circuit (352), a multiplier module (348) for receiving two input values from the crosspoint switch (318) and multiplying the values, and an adder... Agent: Hovey Williams LLP

20080263323 - Reconfigurable computing architectures: dynamic and steering vector methods: A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution... Agent: Dunlap Codding, P.C.

20080263324 - Dynamic core switching: A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when... Agent: Harness, Dickey & Pierce P.L.C

20080263325 - System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor: A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection... Agent: Cantor Colburn LLP-ibm Yorktown

20080263326 - Method and apparatus for an efficient multi-path trace cache design: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.... Agent: Ference & Associates LLC

20080263327 - Automatically selecting firmware instructions for an operating system: Embodiments of the present invention pertain to automatically selecting firmware instructions for an operating system. According to one embodiment, at least a part of a first subset of firmware instructions on a computer system is executed. An automatic determination of whether the first subset of firmware instructions supports an operating... Agent: Hewlett Packard Company

20080263328 - Orthogonal register access: Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263329 - Parallel-prefix broadcast for a parallel-prefix operation on a parallel computer: A parallel-prefix broadcast for a parallel-prefix operation on a parallel computer includes: configuring, on each node, a parallel-prefix contribution buffer for storing the node's parallel-prefix contribution; configuring, on each node, a parallel-prefix results buffer for storing results of a operation, the results buffer having a position for each node that... Agent: Ibm (roc-blf)

20080263330 - Clocked ports: A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port... Agent: Sughrue Mion, PLLC

20080263331 - Universal register rename mechanism for instructions with multiple targets in a microprocessor: A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080263332 - Data processing apparatus and method for accelerating execution subgraphs: A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The... Agent: Nixon & Vanderhye, PC

20080263333 - Document processing method: The present invention discloses a method for processing document data to achieve document interoperation, and the method comprises: by an application, performing an operation on abstract unstructured information by issuing instruction(s) to a platform software; and by the said platform software, receiving the said instruction and performing the operation on... Agent: Ladas & Parry

20080263334 - Dynamically configurable and re-configurable data path: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural... Agent: Stolowitz Ford Cowger, LLP/cypress

20080263336 - Processor having efficient function estimate instructions: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080263335 - Representation of modal intervals within a computer: A modal interval representation having improved computational utility is provided. The modal interval representation generally includes a binary quantifier, and a set theoretical interval for select permutations of marks of a pair of marks of an IEEE standard 754 digital scale. The set theoretical interval includes combinations of real numbers,... Agent: Nawrocki, Rooney & Sivertson Suite 401, Broadway Place East

20080263337 - Instructions for ordering execution in pipelined processes: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution... Agent: Lieberman & Brandsdorfer, LLC

20080263338 - Exception operation apparatus, method and computer program for controlling debugging apparatus, and television and cellular phone providing the same: In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a break point is not set beforehand, a computer, which executes a program to be debugged,... Agent: Birch Stewart Kolasch & Birch

20080263339 - Method and apparatus for context switching and synchronization: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080263340 - Method and device for analyzing a signal from a computer system having at least two execution units: A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to... Agent: Kenyon & Kenyon LLP

20080263341 - Data processing apparatus and method for generating prediction data: A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction... Agent: Nixon & Vanderhye, PC

20080263342 - Apparatus and method for handling exception signals in a computing system: Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and... Agent: Wilmerhale/boston

20080256329 - Multi-magnitudinal vectors with resolution based on source vector features: Methods, systems and computer program products for resolving multiple magnitudes assigned to a target vector are disclosed. A target vector that includes one or more target vector dimensions is received. One of the target vector dimensions is processed to determine a total number of magnitudes assigned to the processed target... Agent: Fish & Richardson, PC

20080256330 - Programming environment for heterogeneous processor resource integration: Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer having a second instruction set architecture, the source... Agent: Intel Corporation C/o Intellevate, LLC

20080256331 - Arithmetic device capable of obtaining high-accuracy calculation results: A plurality of general-purpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied from the general-purpose... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080256332 - Processes and devices for compression and decompression of executable code by a microprocessor with a risc architecture: The invention relates to a process for compression of executable code (2) by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part (BC) of predefined fixed length and a part (VLI) of... Agent: Graybeal, Jackson, Haley LLP

20080256335 - Microprocessor, microcomputer, and electronic instrument: A microprocessor includes a pipeline control section which controls a pipeline process. The pipeline control section decodes an instruction code of an interrupt instruction and causes an immediate generation section to generate a vector address used for referring to information relating to a branch destination address corresponding to the interrupt... Agent: Harness, Dickey & Pierce, P.L.C

20080256334 - Processing system and method for executing instructions: A processing system for executing instructions comprises a first part (11) having address information and a plurality of data bits, Eo to EN. According to one embodiment, each data bit E0 to EN directly selects a corresponding element 130 to 13N forming a second part of the instruction set (for... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080256333 - System and method for ignoring fetch protection: A system, method, and program product is provided that receives an instruction to fetch data from a data page. The data page is associated with a storage key and a fetch protection bit, and the instruction is pointed to by the program status word (PSW) that includes a PSW key... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080256337 - Method of decoding a bit sequence, network element apparatus and pdu specification tool kit: In the field of data communications, it is desirable to track bits of a bit sequence remaining to be decoded by a decoder. A method of decoding the bit sequence that corresponds to a PDU comprises reading-in a bit sequence and processing the bit sequence. In order to maintain a... Agent: Agilent Technologies Inc.

20080256336 - Microprocessor with private microcode ram: A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode.... Agent: Huffman Law Group, P.C.

20080256338 - Techniques for storing instructions and related information in a memory hierarchy: A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The... Agent: Larson Newman Abel Polansky & White, LLP

20080256339 - Techniques for tracing processes in a multi-threaded processor: A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.... Agent: Larson Newman Abel Polansky & White, LLP

20080256340 - Distributed file fuzzing: Embodiments provide a distributed file fuzzing environment. In an embodiment, a number of computing devices can be used as part of a distributing fuzzing system. Fuzzing operations can be distributed to the number of computing devices and processed accordingly. A group or team can be defined to process particular fuzzing... Agent: Merchant & Gould (microsoft)

20080256341 - Data processing pipeline selection: Strategies for automatically selecting the most appropriate processing pipeline (or runtime) for a particular data item are described. In one embodiment, a media playing application automatically selects the most appropriate media processing pipeline for a media data item from multiple available processing pipelines, or candidates. In this regard, the application... Agent: Lee & Hayes PLLC

20080256342 - Scalable and configurable execution pipeline: Optimizing pipeline handler execution. A method may be practiced in a computing environment including an execution pipeline. The method includes acts to optimize execution of handlers in the pipeline. The method includes receiving a payload object. Policy information about the payload object is referenced. The policy information includes at least... Agent: Workman Nydegger/microsoft

20080256343 - Convergence determination and scaling factor estimation based on sensed switching activity or measured power consumption: A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is... Agent: Freedman & Associates

20080256344 - Scan configuration of field programmable gate arrays: Embodiments herein include a method, service, apparatus, etc., that sets at least one integrated circuit board (that has programmable elements) to a programming state. When such programmable elements are set to the programming state, they are capable of being changed. Once the programmable elements are set to be changed, at... Agent: Gibb & Rahman, LLC

20080256346 - Central processing unit having branch instruction verification unit for secure program execution: Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction... Agent: Sughrue Mion, PLLC

20080256345 - Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system: An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve... Agent: Mark P. Kahler

20080256347 - Method, system, and computer program product for path-correlated indirect address predictions: A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted... Agent: Cantor Colburn LLP-ibm Yorktown

20080250224 - System for creating a dynamic ogsi service proxy framework using runtime introspection of an ogsi service: A system for creating a dynamic client side service proxy framework using meta-data and introspection capabilities of Open Grid Services Architecture (OGSA) service data is disclosed. The system includes defining an Open Grid Service Invocation Factory configured to create a service proxy and introspecting an Open Grid Service Infrastructure (OGSI)... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080250225 - Semiconductor device having matrix of processing modules interconnected by local and global self-synchronous buses: A semiconductor device includes a plurality of processing clusters that operate synchronously internally and arranged in a M×N matrix. Each processing cluster is formed as a plurality of processing elements and clocked buses that interconnect the processing elements within each processing cluster. A self-synchronous cluster wrapper is operative with the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist

20080250226 - Multi-mode register rename mechanism for a highly threaded simultaneous multi-threaded microprocessor: A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode,... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080250227 - General purpose multiprocessor programming apparatus and method: The present invention provides methods and apparatus for highly efficient parallel operations using a reduction unit. In a particular aspect, there is provided an apparatus and method for parallel computing. In each of the apparatus and method, there are performed independent operations by a plurality of processing units to obtain... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080250228 - Integrated circuit with restricted data access: A semiconductor integrated circuit includes a hardware mechanism arranged to ensure that associations between instructions and data are enforced so that a processor cannot fetch data from an instruction that is not authorised to do so. A Memory Protection Unit stores entries comprising instructions and associated data memory ranges. A... Agent: Graybeal, Jackson, Haley LLP

20080250229 - System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding: In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache.... Agent: Qualcomm Incorporated

20080250230 - Using a modified value gpr to enhance lookahead prefetch: The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080250231 - Program code conversion apparatus, program code conversion method and recording medium: A program conversion apparatus includes: a code analyzing section configured to analyze an A binary code executable in an A processor in order to convert the A binary code into a program code for a B processor; a instruction function extracting section configured to extract a predetermined instruction function for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080250232 - Data processing device, data processing program, and recording medium recording data processing program: A dependence relationship storage unit M indicates from which input address and input value each of the output addresses and output values derives. An inter-line AND comparator MR performs AND between each of the line components stored in the dependence relationship storage unit M and sets an I/O group including... Agent: Nixon & Vanderhye, PC

20080250233 - Providing thread fairness in a hyper-threaded microprocessor: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements... Agent: Intel Corporation C/o Intellevate, LLC

20080250234 - Microprocessor ouput ports and control of instructions provided therefrom: A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each execution unit. These are scheduled via the microprocessor unit for each execution unit, a determination is made as to whether or not... Agent: Flynn Thiel Boutell & Tanis, P.C.

20080250235 - Microcomputer and method of setting operation of microcomputer: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an... Agent: Mcginn Intellectual Property Law Group, PLLC

20080244220 - Filter and method for filtering: P

20080244221 - Exposing system topology to the execution environment: Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the... Agent: Intel Corporation C/o Intellevate, LLC

20080244222 - Many-core processing using virtual processors: The present disclosure provides a method for virtual processing. According to one exemplary embodiment, the method may include partitioning a plurality of cores of an integrated circuit (IC) into a plurality of virtual processors, the plurality of virtual processors having a framework dependent upon a programming application. The method may... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20080244223 - Branch pruning in architectures with speculation support: According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since... Agent: Schwegman, Lundberg & Woessner, P.A.

20080244224 - Scheduling a direct dependent instruction: In one embodiment, the present invention includes an apparatus having an instruction selector to select an instruction, where the selector is to store a dependent indicator to indicate a direct dependent consumer instruction of a producer instruction, a decode logic coupled to the instruction selector to receive the dependent indicator... Agent: Trop Pruner & Hu, PC

20080244225 - Integrated circuit and method for transaction retraction: An integrated circuit having a plurality of processing modules (I, T) is provided. At least one first processing module (I) issues at least one transaction towards at least one second processing module (T). Said integrated circuit further comprises at least one first transaction retraction unit (TRU1) for indicating an allowance... Agent: Philips Intellectual Property & Standards

20080244227 - Design structure for asymmetrical performance multi-processors: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, for allocating processing functions between a primary processor and a secondary processor is disclosed. A primary processor is provided that performs routine processing duties, including execution of application program code, while the secondary... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080244226 - Thread migration control based on prediction of migration overhead: A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory (RAM) responsive to the first and second processing cores. The processing system also features control logic to perform operations such as (a)... Agent: Intel Corporation C/o Intellevate, LLC

20080244228 - Electronic device with an array of processing units: The invention concerns electronics devices like X-ray detectors with an array of pixels (303) that can be combined (binned) into binning blocks of m×n pixels. According to the invention the available read-out lines (325) of the device are all connected to different binning blocks in each read-out step, such that... Agent: Philips Intellectual Property & Standards

20080244229 - Information processing apparatus: In an information processing apparatus, a fetch to a storage address of a first storage unit which stores a first instruction executed at first within a plurality of instructions that is included in a software and executed when a processor starts the software via the channel is detected. It is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080244230 - Scalable processing architecture: A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an... Agent: Winstead PC

20080244231 - Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine: In some embodiments, the invention involves a novel combination of techniques for prefetching data and passing messages between and among cores in a multi-processor/multi-core platform. In an embodiment, a receiving core has a message queue and a message prefetcher. Incoming messages are simultaneously written to the message queue and the... Agent: Intel Corporation C/o Intellevate, LLC

20080244232 - Pre-fetch apparatus: Apparatus and computing systems associated with data pre-fetching are described. One embodiment includes a processor that includes a first unit to store data corresponding to a load instruction and an instruction pointer (IP) value associated with the load instruction. The processor also includes a second unit to produce a predicted... Agent: Kraguljac & Kalnay, LLC

20080244233 - Machine cluster topology representation for automated testing: Software (such as server products) operating in a complex networked environment often run on multi-machine installations that are known as machine clusters. A server product can be tested on a server machine type. The server product can be tested by tracking the constituent machines of a machine cluster, and configuring... Agent: Merchant & Gould (microsoft)

20080244235 - Circuit marginality validation test for an integrated circuit: A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and bubble logic in the front end to provide flexibility in binding a port to the uop and to create empty spaces (bubbles) in the uop... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080244234 - System and method for executing instructions prior to an execution stage in a processor: A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly... Agent: Qualcomm Incorporated

20080244237 - Compute unit with an internal bit fifo circuit: A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to... Agent: Iandiorio & Teska

20080244239 - Method and system for autonomic monitoring of semaphore operations in an application: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080244236 - Method and system for composing stream processing applications according to a semantic description of a processing goal: A method for assembling a stream processing application, includes: inputting a plurality of data source descriptions, wherein each of the data source descriptions includes a graph pattern that semantically describes an output of a data source; inputting a plurality of component descriptions, wherein each of the component descriptions includes a... Agent: F. Chau & Associates, LLC

20080244238 - Stream processing accelerator: The present invention is a stream processing accelerator which includes multiple coupled processing elements which are interconnected through a shared file register and a set of global predicates. The stream processing accelerator has two modes: full-processor mode and circuit mode. In full-processor mode, a branch unit, an arithmetic logic unit... Agent: Haverstock & Owens LLP

20080244240 - Semiconductor device: A semiconductor device includes a first arithmetic engine which executes a first arithmetic process in every cycle and outputs first data representing the result of the first arithmetic process and a first valid signal representing a first or second value in every cycle, and a second arithmetic engine which executes... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080244241 - Handling floating point operations: A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive subject code instructions including at least one instruction relating to a floating... Agent: Wilmerhale/boston

20080244243 - Computer program product and system for altering execution flow of a computer program: A debugger alters the execution flow of a child computer program of the debugger at runtime by inserting jump statements determined by the insertion of breakpoint instructions. Breakpoints are used to force the child computer program to throw exceptions at specified locations. One or more instructions of the computer program... Agent: Ibm Endicott (anthony England) Law Office Of Anthony England

20080244242 - Using a register file as either a rename buffer or an architected register file: A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080244244 - Parallel instruction processing and operand integrity verification: A method includes accessing, at a processing device, operand data associated with an instruction operation from a data cache and executing, at the processing device, the instruction operation using the operand data prior to determining the validity of the operand data. The method further includes retiring, at the processing device,... Agent: Larson Newman Abel Polansky & White, LLP

20080244245 - Optimal selection of compression entries for compressing program instructions: A method of compressing instructions in a program may include extracting unique bit patterns from the instructions in the program and constructing a linear programming formulation or an integer programming formulation from the unique bit patterns, the instructions, and/or the size of a memory storage. The linear programming formulation or... Agent: Trop, Pruner & Hu, P.C.

20080244246 - Integrated mpe-fec ram for dvb-h receivers: A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM... Agent: Gibb & Rahman, LLC

20080244247 - Processing long-latency instructions in a pipelined processor: There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed... Agent: Flynn Thiel Boutell & Tanis, P.C.