|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) September archived by title and patent number 09/08Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/25/2008 > patent applications in patent subcategories. archived by title and patent number
20080235490 - System for configuring a processor array: Embodiments of the invention are directed to a system for configuring a processor array using configuration chains streamed down communication channels.... Agent: Ambric, Inc. C/o Marger Johnson & Mccollom PC
20080235491 - Techniques for maintaining a stack pointer: A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then... Agent: Larson Newman Abel Polansky & White, LLP
20080235492 - Apparatus for compressing instruction word for parallel processing vliw computer and method for the same: An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each... Agent: Sughrue Mion, PLLC
20080235493 - Instruction communication techniques for multi-processor system: A method for communicating instructions to slave processors in a multi-processor system having a master processor and pipelined slave processors controlled by the master processor is described. The method uses a pass-through command having (i) a header block coded using a computer language understood by the slave processors and (ii)... Agent: Qualcomm Incorporated
20080235494 - Musical instrument digital interface hardware instruction set: Generating a digital waveform for a Musical Instrument Digital Interface (MIDI) voice using a set of machine-code instructions that is specialized for the generation of digital waveforms for MIDI voices. For example, a processor may execute a software program that generates a digital waveform for a MIDI voice. The instructions... Agent: Qualcomm Incorporated
20080235495 - Method and apparatus for counting instruction and memory location ranges: A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080235496 - Methods and apparatus for dynamic instruction controlled reconfigurable register file: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For... Agent: Peter H. Priest
20080235497 - Parallel data output: Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an... Agent: Mentor Graphics Corp. Patent Group
20080235498 - Test apparatus and electronic device: There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with... Agent: Jianq Chyun Intellectual Property Office
20080235499 - Apparatus and method for information processing enabling fast access to program: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the... Agent: Kaplan Gilman Gibson & Dernier L.L.P.
20080235500 - Structure for instruction cache trace formation: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-109/18/2008 > patent applications in patent subcategories. archived by title and patent number
20080229058 - Configurable microprocessor: A configurable microprocessor that handles low computing-intensive workloads by partitioning a single processor core into two smaller corelets. The process partitions resources of a single microprocessor core to form a plurality of corelets and assigns a set of the partitioned resources to each corelet. Each set of partitioned resources is... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080229059 - Message routing scheme: Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address... Agent: Sughrue Mion, PLLC
20080229060 - Micro controller and method of updating the same: A micro controller includes a first storing circuit configured to store program data for performing a power on operation of a system, and a second storing circuit configured to temporarily store algorithm program data for operation of the system loaded from an external storing means while the system operates in... Agent: Townsend And Townsend And Crew, LLP
20080229061 - Processor element for use in a network of processor elements: In order to detect objects using a processor element for use in a network of processor elements which are connected to one another, the processor element comprises a processor, at least one interface for coupling to further processor elements of the network and an oscillator having a connection for coupling... Agent: Infineon Technologies Ag Patent Department
20080229062 - Method of sharing registers in a processor and processor: A method of sharing registers in a processor includes executing a data processing instruction so as to obtain a result of the data processing instruction, which is to be written into a register of the processor. Register sharing information is obtained so as to control writing of the result into... Agent: Slater & Matsil LLP
20080229063 - Processor array with separate serial module: A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines... Agent: Philips Intellectual Property & Standards
20080229064 - Package designs for fully functional and partially functional chips: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the... Agent: Osha Liang L.L.P./sun
20080229065 - Configurable microprocessor: A configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads. The process first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080229066 - System and method for compiling scalar code for a single instruction multiple data (simd) execution engine: A system, method, and computer program product are provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20080229068 - Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches: A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown
20080229067 - Data pointers with fast context switching: An apparatus and method are disclosed for multiple data pointer registers and a means for quickly switching active context between the data pointer registers.... Agent: Fish & Richardson P.C.
20080229070 - Cache circuitry, data processing apparatus and method for prefetching data: Cache circuitry, a data processing apparatus including such cache circuitry, and a method for prefetching data into such cache circuitry, are provided. The cache circuitry has a cache storage comprising a plurality of cache lines for storing data values, and control circuitry which is responsive to an access racquet issued... Agent: Nixon & Vanderhye, PC
20080229071 - Prefetch control apparatus, storage device system and prefetch control method: A prefetch control apparatus includes a prefetch controller for controlling prefetch of read data into a cache memory caching data to be transferred between a computer apparatus and a storage device, and which enhances a read efficiency of the read data from the storage device, a sequentiality decider for deciding... Agent: Staas & Halsey LLP
20080229072 - Prefetch processing apparatus, prefetch processing method, storage medium storing prefetch processing program: A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing... Agent: Greer, Burns & Crain
20080229069 - System, method and software to preload instructions from an instruction set other than one currently executing: An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI... Agent: Qualcomm Incorporated
20080229073 - Address calculation and select-and insert instructions within data processing systems: A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon... Agent: Nixon & Vanderhye, PC
20080229074 - Design structure for localized control caching resulting in power efficient control logic: A design structure for an integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized... Agent: Downs Rachlin Martin PLLC
20080229075 - Microcontroller with low-cost digital signal processing extensions: A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.... Agent: Fish & Richardson P.C.
20080229076 - Macroscalar processor architecture: A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that... Agent: Blakely Sokoloff Taylor & Zafman LLP
20080229077 - Computer processing system employing an instruction reorder buffer: A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after... Agent: Cantor Colburn LLP-ibm Yorktown
20080229078 - Dynamic power management in a processor design: Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20080229079 - Apparatus, system, and method for managing commands of solid-state storage using bank interleave: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state... Agent: Kunzler & Mckenzie
20080229080 - Arithmetic processing unit: An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller.... Agent: Staas & Halsey LLP
20080229081 - Reconfigurable circuit, reconfigurable circuit system, and reconfigurable circuit setting method: Each cell comprises a first selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; a second selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single... Agent: Mcdermott Will & Emery LLP
20080229082 - Control sub-unit and control main unit: A sub-unit judges whether an instruction received from an external unit is executable. If the instruction is judged to be executable, the sub-unit executes it. If, on the other hand, the instruction is judged to be unexecutable, the sub-unit notifies the external unit of an executable plan.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080229083 - Processor instruction set: The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the... Agent: Sughrue Mion, PLLC
20080229084 - Method of determing request transmission priority subject to request channel and transtting request subject to such request transmission priority in application of fieldbus communication framework: A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is... Agent: Moxa Technologies Co., Ltd09/11/2008 > patent applications in patent subcategories. archived by title and patent number
20080222388 - Simulation of processor status flags: The dynamic efficient and accurate simulation of processor status flags is described. One exemplary embodiment includes simulation of processor status flags of a first CPU type on a second CPU type using simple arithmetic operations to calculate status flags in parallel, and by keeping an intermediate state that allows efficient... Agent: Microsoft Corporation
20080222389 - Interprocessor message transmission via coherency-based interconnect: A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information.... Agent: Larson Newman Abel Polansky & White, LLP
20080222390 - Low noise coding for digital data interface: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest... Agent: Texas Instruments Incorporated
20080222391 - Apparatus and method for optimizing scalar code executed on a simd engine by alignment of simd slots: An apparatus and method for optimizing scalar code executed on a single instruction multiple data (SIMD) engine is provided that aligns the slots of SIMD registers. With the apparatus and method, a compiler is provided that parses source code and, for each statement in the program, generates an expression tree.... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.
20080222392 - Method and arrangements for pipeline processing of instructions: In one embodiment a method for parallel processing in a processing pipeline is disclosed. The method can include determining that a jump instruction is loaded in a main path of a processing pipeline prior to the jump instruction being executed. The method can load a jump hit target instruction in... Agent: Alan Carlson
20080222393 - Method and arrangements for pipeline processing of instructions: In one embodiment a method for operating a processing pipeline is disclosed. The method can include fetching an instruction in a first clock cycle, decoding the instruction in a second clock cycle and fetching an instruction data associated with the instruction in the second clock cycle. The method can also... Agent: Alan Carlson
20080222394 - Systems and methods for tdm multithreading: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson Pllc
20080222397 - Hard object: hardware protection for software objects: In accordance with one embodiment, additions to the standard computer microprocessor architecture hardware are disclosed comprising novel page table entry fields 015 062, special registers 021 022, instructions for modifying these fields 120 122 and registers 124 126, and hardware-implemented 038 runtime checks and operations involving these fields and registers.... Agent: Daniel Wilkerson
20080222396 - Low overhead access to shared on-chip hardware accelerator with memory-based interfaces: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged... Agent: Mhkkg/sun
20080222395 - System and method for predictive early allocation of stores in a microprocessor: A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20080222398 - Programmable processor with group floating-point operations: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at... Agent: Mcdermott Will & Emery LLP
20080222399 - Method for the handling of mode-setting instructions in a multithreaded computing environment: The present invention relates to the provisioning of mode-setting instruction as they relate to requisite hardware within a processing system. As such, the processing system allows for multiple programs, or processing threads of execution, to independently specify Modes, wherein modes are program specified assertions in regard to the processing system... Agent: Cantor Colburn LLP-ibm Yorktown
20080222400 - Power consumption of a microprocessor employing speculative performance counting: Reduction of power consumption and chip area of a microprocessor employing speculative performance counting, comprising splitting a counter and a backup register of a speculative counting mechanism performing the speculative performance counting into first and second parts each, re-using an available storage within the microprocessor as first parts respectively; integrating... Agent: International Business Machines Corporation
20080222401 - Method and system for enabling state save and debug operations for co-routines in an event-driven environment: A method of enabling state save and debug operations for co-routines for first failure data capture (FFDC) in an event-driven environment. A stack management utility allocates space for a context structure, which includes a state field, and a stack pointer in a buffer. A context management utility initializes a first... Agent: Dillon & Yudell, LLP09/04/2008 > patent applications in patent subcategories. archived by title and patent number
20080215850 - Systems, methods and apparatus for local programming of quantum processor elements: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.... Agent: Seed Intellectual Property Law Group PLLC
20080215851 - Method and arrangement for the power-efficient control of processors: A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied... Agent: Baker Botts L.L.P.
20080215852 - System and device architecture for single-chip multi-core processor having on-board display aggregator and i/o device selector control: System, device, device architecture, and method for operating a multi-core processor providing application level file isolation and providing display frame buffer aggregator or selector to provide a user with the experience of multiple simultaneous application execution within a single processor while actually providing separate concurrent but isolated processing sessions.... Agent: Perkins Coie LLP
20080215853 - System and method for line rate frame processing engine using a generic instruction set: A system comprises a frame parser and lookup engine operable to receive an incoming data frame, extract control data from payload data in the data frame, and using the control data to access a memory to fetch a plurality of instructions, a destination and tag management module operable to receive... Agent: Haynes And Boone, LLP
20080215854 - System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor... Agent: Frank Chau, Esq. F. Chau & Associated, LLC
20080215855 - Execution unit for performing shuffle and other operations: In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such... Agent: Trop Pruner & Hu, PC
20080215857 - Method for latest producer tracking in an out-of-order processor, and applications thereof: Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20080215856 - Methods for generating code for an architecture encoding an extended register specification: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.... Agent: Keusey, Tutunjian & Bitetto, P.C.
20080215858 - Processor and program execution method capable of efficient program execution: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution... Agent: Snell & Wilmer L.L.P. (matsushita)
20080215859 - Computer with high-speed context switching: A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area... Agent: Staas & Halsey LLP
20080215861 - Method and apparatus for efficient resource utilization for prescient instruction prefetch: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20080215860 - Software protection using code overlapping: Apparatus and methods for implementing software protection using code overlapping are disclosed. In one implementation, a combination block comprising a first sub-block of instructions with one or more interspersed obfuscation instructions is received. The obfuscation instructions interspersed among sequentially executable instructions of the first sub-block of instructions can include instructions... Agent: Lee & Hayes PLLC
20080215863 - Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20080215862 - Program creation device, program test device, program execution device, information processing system: The present invention comprises a program generation apparatus for generating an obfuscated program difficult to analyze from outside and a program execution apparatus for executing the program. The program generation apparatus comprises: an acquisition unit operable to acquire a 1st program including one or more instructions, the 1st program causing... Agent: Wenderoth, Lind & Ponack L.L.P.
20080215864 - Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor: A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for... Agent: Kenyon & Kenyon LLP
20080215865 - Data processor and memory read active control method: Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the... Agent: Staas & Halsey LLP
20080215866 - Branch prediction apparatus, systems, and methods: An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.Previous industry: Electrical computers and digital processing systems: memory
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