Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 08/08

20080209162 - Processor and program execution method capable of efficient program execution: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution... Agent: Snell & Wilmer L.l.p. (matsushita)

20080209163 - Data processing system with backplane and processor books configurable to suppprt both technical and commercial workloads: A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided... Agent: Dillon & Yudell LLP

20080209164 - Microprocessor architectures: A microprocessor architecture comprises a plurality of processing elements arranged in a single instruction multiple data SIMD array, wherein each processing element includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, a serial processor which includes a plurality of... Agent: Welsh & Katz, Ltd

20080209165 - Simd microprocessor, image processing apparatus including same, and image processing method used therein: A SIMD microprocessor, which can be included in an image processing apparatus using an image processing method used therein, includes a global processor and multiple processor elements controlled by the global processor. Each single processor element of the multiple processor elements includes multiple operation units. The global processor is configured... Agent: Dickstein Shapiro LLP

20080209166 - Method of renaming registers in register file and microprocessor thereof: A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one... Agent: F. Chau & Associates, Llc

20080209167 - Apparatus and method for adaptive multimedia reception and transmission in communication environments: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media... Agent: Nixon Peabody, LLP

20080209168 - Information processing apparatus, process control method, and computer program: A method and apparatus for improving data processing efficiency with an improved context storage mechanism are provided. In an arrangement where data processing is performed with a plurality of logical processors are allocated to a physical process in a time sharing manner, a context table of a logical processor with... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080209169 - Output stage circuit apparatus for a processor device and method therefor: A drive circuit arrangement for a processor device comprises a non-volatile register for recording the identities of outputs of the processor device at which a same output signal is required. Configuration circuitry employs dual pairs of switching devices to couple register locations associated with a predetermined output of the processor... Agent: Freescale Semiconductor, Inc. Law Department

20080209170 - Method and device for performing switchover operations and for signal comparison in a computer system having at least two processing units: A method for switchover and for signal comparison is used in a computer system having at least two processing units, a switchover device being provided, and a switch taking place between at least two operating modes, and a comparison device being provided; and a first operating mode corresponds to a... Agent: Kenyon & Kenyon LLP

20080209171 - System and method for managing a register-based stack of operand tags: A virtual machine in a processing system manages type information for operands. In one embodiment, the virtual machine accomplishes the following results through execution of a single instruction: adding an operand tag to a tag stack, and updating a stack pointer for the tag stack to recognize the addition of... Agent: Intel Corporation C/o Intellevate, Llc

20080209172 - Selective hardware lock disabling: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire... Agent: Kraguljac & Kalnay, Llc

20080209173 - Branch predictor directed prefetch: An apparatus for executing branch predictor directed prefetch operations. During operation, a branch prediction unit may provide an address of a first instruction to the fetch unit. The fetch unit may send a fetch request for the first instruction to the instruction cache to perform a fetch operation. In response... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080209175 - Computer system and method of adapting a computer system to support a register window architecture: A target computing system 10 is adapted to support a register window architecture, particularly for use when converting non-native subject code 17 instead into target code 21 executed by a target processor 13. A subject register stack data structure (an “SR stack”) 400 in memory has a plurality of frames... Agent: Wilmerhale/boston

20080209174 - Processor and its instruction issue method: An instruction issue method for use in a pipelined processor, comprising the steps of: decoding an instruction to be processed to get a type of the instruction; computing the number of cycles to be occupied at execution stage for the instruction, according to the type of the instruction; marking a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080209177 - Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch: A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080209178 - Method and apparatus for back to back issue of dependent instructions in an out of order issue queue: A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080209176 - Time stamping transactions to validate atomic operations in multiprocessor systems: A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080209180 - Emulation prevention byte removers for video decoder: An emulation prevention byte remover may include one or more of a first buffer, a second buffer, a checker, and a shifter. The first buffer may store first stream data. The second buffer may store second stream data. The checker may determine whether one or more emulation prevention bytes are... Agent: Harness, Dickey & Pierce, P.L.C

20080209179 - Low-impact performance sampling within a massively parallel computer: An apparatus, program product and method sample at different times nodes that are performing similar work. Performance data associated with first and second node subsets performing the similar work are sampled at different times, e.g., in a round-robin fashion, and in accordance with a given sampling rate. The performance data... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080209181 - Method and system for automatic generation of processor datapaths: Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080209182 - Multi-mode data processing device and methods thereof: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data... Agent: Larson Newman Abel Polansky & White, LLP

20080209183 - Fast sparse list walker: Provided are a method, information processing system, and computer readable medium for identifying active bits in a vector. The method comprises receiving a pointer associated with a vector of bits. The pointer is associated with a current bit within the vector of bits. The vector of bits if grouped into... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20080209184 - Processor with reconfigurable floating point unit: A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations,... Agent: Larson Newman Abel Polansky & White, LLP

20080209185 - Processor with reconfigurable floating point unit: A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or... Agent: Larson Newman Abel Polansky & White, LLP

20080209186 - Method for reducing buffer capacity in a pipeline processor: The invention presents a method for a processor (1), and a processor comprising a processing pipeline (2) and at least one interface (3) for data packets. The method is characterized by giving a second data packet (D2) admittance to the pipeline (2) in dependence on cost information (c1), dependent upon... Agent: Greenberg Traurig, LLP

20080209187 - Storing and processing simd saturation history flags and data size: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturation operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data... Agent: Oliff & Berridge, Plc

20080209189 - Information processing apparatus: The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction... Agent: Staas & Halsey LLP

20080209188 - Processor and method of performing speculative load operations of the processor: Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that... Agent: Sughrue Mion, Pllc

20080209190 - Parallel prediction of multiple branches: A branch history value associated with a first branch instruction of a first set of instructions is determined. The branch history value represents a branch history of a program flow prior to the first branch instruction. A first branch prediction of the first branch instruction is determined based on the... Agent: Larson Newman Abel Polansky & White, LLP

20080209191 - Nested exception roles: A method and apparatus for managing a nested EXCEPTION role in a directory server is described. In one embodiment, a plurality of entries is defined in the directory server. At least one of the plurality of entries possesses a role. An entry is queried to determine its possessed role. A... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080209192 - Processor and program execution method capable of efficient program execution: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution... Agent: Snell & Wilmer L.l.p. (matsushita)

20080201554 - Optional function multi-function instruction: A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query... Agent: International Business Machines Corporation

20080201555 - Image processing apparatus, method for controlling image processing apparatus, control program, and recording medium: An image processing apparatus is disclosed that includes an image processing unit section and an information processing unit section. The image processing unit section includes an image scanner that performs an image processing function and a SDK application that expands and controls the function of the image processing apparatus. The... Agent: Harness, Dickey & Pierce, P.L.C

20080201556 - Program instruction rearrangement methods in computer: A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and rearranging instructions based on the dependency depth. Additionally, the dependency between instructions can be utilized to locate and remove redundant instructions.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080201558 - Processor system: A processor system according to an aspect of the present invention has a pipeline. The pipeline includes a cache memory, an instruction fetch buffer which stores commands, an execution module which requests data access to the cache memory, a tag memory which outputs information related to the data access of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080201557 - Security message authentication instruction: A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an authentication code is to be computed. An computing operation computes an authentication code for the unit of storage. A... Agent: International Business Machines Corporation

20080201559 - Switching device and corresponding method for activating a load: A cost-effective safety concept for safety-relevant applications in motor vehicles accordingly activates a load not directly from a central unit, but instead indirectly via a switching device. The latter has a first and a second register for the acquisition of the same control data from the central unit, and a... Agent: Lerner Greenberg Stemer LLP

20080201560 - Very long instruction word (vliw) computer having efficient instruction code format: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very... Agent: Wenderoth, Lind & Ponack L.L.P.

20080201561 - Multi-threaded parallel processor methods and apparatus: A processor system, a processor readable medium and a method for implementing multiple contexts on one or more SPE are disclosed.... Agent: Joshua D. Isenberg Jdi Patent

20080201563 - Apparatus for improving single thread performance through speculative processing: An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080201562 - Data processing system: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a... Agent: Miles & Stockbridge PC

20080201564 - Data processor: An object of the present invention is to achieve fast data processing. A unit (FF) is included for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether... Agent: Miles & Stockbridge PC

20080201565 - Context switch data prefetching in multithreaded computer: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread,... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080201566 - Method and apparatus for measuring pipeline stalls in a microprocessor: A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080201567 - Method of doing pack unicode zseries instructions: Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080195841 - Driving apparatus of display device and driving method thereof: Disclosed is a driving apparatus of a display device having a plurality of pixels. The driving apparatus includes a signal generator that generates a shutdown signal, first and second register units that store register values, a gate driver that transmits gate signals to the pixels, a data driver that transmits... Agent: Macpherson Kwok Chen & Heid LLP

20080195840 - Identifying messaging completion on a parallel computer: Methods, parallel computers, and products are provided for identifying messaging completion on a parallel computer. The parallel computer includes a plurality of compute nodes, the compute nodes coupled for data communications by at least two independent data communications networks including a binary tree data communications network optimal for collective operations... Agent: Ibm (roc-blf)

20080195839 - Reconfigurable, modular and hierarchical parallel processor system: The invention concerns a method for managing resources of a modular processor system comprising the following steps of transmitting an instruction of a programme contained in a first machine with higher level status to a second machine with lower level status to manage the running of the programme; attributing links... Agent: Drinker Biddle & Reath Attn: Intellectual Property Group

20080195842 - Array-type processor: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a... Agent: Sughrue Mion, Pllc

20080195843 - Method and system for processing a volume visualization dataset: A method of processing a volume visualization dataset. Information is transmitted from a resource manager to a task scheduling module regarding the number of processor nodes and amount of storage available in associated storage devices, and sub-tasks instructions including algorithm modules are transmitted from the task scheduling module to a... Agent: Law Office Of Delio & Peterson, Llc.

20080195844 - Redirect recovery cache: In one embodiment, a processor comprises a branch resolution unit and a redirect recovery cache. The branch resolution unit is configured to detect a mispredicted branch operation, and to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080195845 - Data processing system having flexible instruction capability and selection mechanism: If a data processing system (10) implements more than one instruction set within a single processor (12), then program portions encoded using a first instruction set will need to be able to call program portions encoded using a second instruction set. This switching between instruction sets requires that the processor... Agent: Freescale Semiconductor, Inc. Law Department

20080195846 - Distributed dispatch with concurrent, out-of-order dispatch: In one embodiment, a processor comprises an instruction buffer and a pick unit. The instruction buffer is coupled to receive instructions fetched from an instruction cache. The pick unit is configured to select up to N instructions from the instruction buffer for concurrent transmission to respective slots of a plurality... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080195847 - Aggressive loop parallelization using speculative execution mechanisms: A system and method for aggressive loop parallelization using speculative execution is disclosed. The method may include transforming code of a target application for concurrent execution, which may include adding an instruction to create a global address table entry for each store operation on which a load operation of a... Agent: Mhkkg/sun

20080195848 - Vertical and horizontal pipelining in a system for performing modular multiplication: The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the... Agent: International Business Machines Corporation

20080195849 - Cache sharing based thread control: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a... Agent: Kraguljac & Kalnay, Llc

20080195850 - Method and system for restoring register mapper states for an out-of-order microprocessor: A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table... Agent: Dillon & Yudell LLP

20080195851 - Multi-threaded processor: A multi-threaded processor comprises a processing unit (PU) for concurrently processing multiple threads. A register file means (RF) is provided having a plurality of registers, wherein a first register (LI) is used for storing loop invariant values and N second registers (LVI-LVN) are each used for storing loop variant values.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080189512 - Processor for executing switch and translate instructions requiring wide operands: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP

20080189513 - Vector processing: p

20080189514 - Reconfigurable logic in processors: A data processor comprises an array of processing elements (PEn 4), each element in the array comprising a respective configurable logic unit (CLU 11), whereby the logic capability of each processing element can be reconfigured at will. Memory (14, FIGS. 3, 4 not shown) may be pre-loaded with configuration instructions,... Agent: Welsh & Katz, Ltd

20080189515 - Electronic parallel processing circuit: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements... Agent: Philips Intellectual Property & Standards

20080189516 - Using ir drop data for instruction thread direction: A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit including an adaptive power supply which provides, among other data, IR (voltage) drop information. Circuitry is provided that receives the IR drop information from the many central processing... Agent: Ibm Corporation

20080189517 - Using temperature data for instruction thread direction: A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit includes an adaptive power supply which provides, among other data, temperature information. Circuitry is provided that receives the temperature information from the many central processing units, selects a... Agent: Ibm Corporation

20080189518 - Processor instruction cache with dual-read modes: A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to... Agent: Harness, Dickey & Pierce P.L.C

20080189519 - Implementing instruction set architectures with non-contiguous register file specifiers: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080189521 - Speculative instruction issue in a simultaneously multithreaded processor: A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the... Agent: Duke W. Yee Yee & Associates, P.C.

20080189520 - Using performance data for instruction thread direction: A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the method having steps of receiving internal performance data signals from a pool... Agent: Ibm Corporation

20080189523 - Calculation apparatus provided with a plurality of calculating units which access a single memory: A calculation apparatus comprises a plurality of processing units that processes a plurality of predetermined calculation processes each composed of steps, respectively, and a memory device to which the plurality of processing units are accessible. Specific information that specifies a step that should be executed next among steps of each... Agent: Nixon & Vanderhye, PC

20080189522 - Method and apparatus for enabling resource allocation identification at the instruction level in a processor system: An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor hardware unit initiating a system bus request with a... Agent: Mark P. Kahler

20080189524 - Configurable shader alu units: A shader unit is configured to provide an increased and dynamically changeable amount of ALU processing bandwidth. The shader unit includes a plurality of ALUs for processing pixel data according to a shader program. Each of the ALUs is configurable to be enabled and disabled. When disabled, the ALU is... Agent: Haverstock & Owens LLP

20080189525 - Implementing a two phase open firmware driver in adapter fcode: A computer implemented method, data processing system, and computer usable program code are provided for implementing a two phase open firmware driver. A computer system probes a device for a dummy image that uses open firmware code in a compiled format. The computer system executes the dummy image. The dummy... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080189526 - Dynamic modifier function blocks for use in a process control system: Dynamic modifier function blocks for use in a process control system are disclosed. In accordance with one aspect, an example function block is stored on a machine readable medium for use in a process control system. The example function block includes a base function block that causes a machine to... Agent: Hanley, Flight & Zimmerman, LLC

20080189527 - Employing a buffer to facilitate instruction execution: Instruction execution is facilitated by employing a buffer to handle instructions having special circumstances. When such an instruction is to be executed, a pointer of the instruction is directed to the buffer. The instruction is executed from the buffer and then the pointer is recovered to point to a location... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080189528 - System, method and software application for the generation of verification programs: A system, method and software application according to the present invention creates complex, interesting, self checking and sturdy verification programs. A self-checking random verification program automatically generates appropriate register and memory reference values, inserts checkpoints and gathers and reports results to test CPU designs. With appropriate templates and simulator, the... Agent: Legal Department Mips Technologies, Inc.

20080189529 - Controlling instruction execution in a processing environment: Instruction execution is controlled by a single test that determines whether processing should continue in mainline processing or fall through to a test set. The single test compares a dynamically set variable to an instruction counter. If the test is met, mainline processing continues. Otherwise, processing falls through to a... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080189530 - Method and system for hardware based program flow monitor for embedded software: A method for malware detection, wherein the method includes: utilizing a hardware based program flow monitor (PFM) for embedded software that employs a static analysis of program code; marrying the program code to addresses, while considering which central processing unit (CPU) is executing the program code; capturing an expected control... Agent: Cantor Colburn LLP-ibm Yorktown

20080189531 - Preventing register data flow hazards in an sst processor: One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080189532 - Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced state viterbi detector: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an... Agent: Ryan, Mason & Lewis, LLP Suite 205

20080189533 - Method, system and apparatus for generation of global branch history: Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set... Agent: SprinkleIPLaw Group

20080189534 - Apparatus and method for policy-driven business process exception handling: A model-driven and QoS-aware infrastructure facilitates the scalable composition of Web services in highly dynamic environments. An exception management framework supports two modes of exception management for business processes, providing a novel policy-driven approach to exception management implemented in the system infrastructure. Exception management is implemented in the system infrastructure,... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080189535 - Method and system for dependency tracking and flush recovery for an out-of-order microprocessor: A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of the particular logical register and recording, in a next DEF... Agent: Dillon & Yudell LLP