Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 07/08

20080184007 - Method and system to combine multiple register units within a microprocessor: A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register... Agent: Qualcomm Incorporated

20080184008 - Delegating network processor operations to star topology serial bus interfaces: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor... Agent: Zilka-kotab, PC- Rmi

20080184009 - Shared resources in a chip multiprocessor: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080184010 - Method and apparatus for controlling instruction cache prefetch: According to the present invention, there is provided an instruction cache prefetch control apparatus having an external memory, a CPU and an instruction cache unit, the instruction cache unit having: an instruction cache data memory which receives and stores the instruction sequence; a prefetch buffer which prefetches and stores an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080184011 - Speculative throughput computing: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to translate a program to execute on a plurality of processors, processor cores, or threads.... Agent: Fish & Richardson P.C.

20080184012 - Speculative throughput computing: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to reduce a number of miss-speculations during execution of program segments in parallel.... Agent: Fish & Richardson P.C.

20080184013 - Print setting instructing device, information processor, printing process system, print setting instructing system, print setting instructing method, and computer readable medium: A print setting instructing device includes: a receiving unit that receives a first control instruction, which shows a print condition, embedded in a printed; a determining unit that determines whether or not the first control instruction received by the receiving unit needs to be converted into a second control instruction;... Agent: Oliff & Berridge, PLC

20080184015 - Data processing system and method: A method of optimizing a thread in a system comprising a plurality of processors, the method comprising: determining performance of the thread on each of the processors; comparing the determined performances; and selecting a processor for executing the thread based on the comparison.... Agent: Hewlett Packard Company

20080184014 - Method for efficiently emulating computer architecture condition code settings: Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080184016 - Architectural support for software-based protection: Instruction set architecture (ISA) extension support is described for control-flow integrity (CFI) and for XFI memory protection. ISA replaces CFI guard code with single instructions. ISA support is provided for XFI in the form of bounds-check instructions. Compared to software guards, hardware support for CFI and XFI increases the efficiency... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080184017 - Parallel data processing apparatus: A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements, comprises determining which instruction stream has priority at a particular moment in time, and transferring that instruction stream to the SIMD array.... Agent: Glenn Patent Group

20080184018 - Speculative throughput computing: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to execute program segments in parallel.... Agent: Fish & Richardson P.C.

20080184019 - Method for embedding short rare code sequences in hot code without branch-arounds: The problem of handling exceptionally executed code portions is improved through the practice of embedding handling instructions within other instructions, such as within their “immediate” fields. Such instructions are chosen to have short execution times. Most of the time these instructions are executed quickly without having to include jumps around... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080177979 - Hardware multi-core processor optimized for object oriented computing: A multi-core processor system includes a context area, which contains an array of stack core processing elements, a storage area that contains expensive shared resources (e.g., object cache, stack cache, and interpretation resources), and an execution area, which contains complex execution units such as an FPU and a multiply unit.... Agent: Mccormick, Paulding & Huber LLP

20080177981 - Apparatus and method for decreasing the latency between instruction cache and a pipeline processor: A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream.... Agent: Connolly Bove Lodge & Hutz LLP

20080177980 - Instruction set architecture with overlapping fields: A system and corresponding methods that facilitate implementing and decoding variable size instruction fields in a fixed size instruction are provided. In accordance with one aspect of the invention, an instruction has one or more instructions fields, wherein each field is represented by a plurality of bits arranged in a... Agent: Stephen C. Kaufman Ibm Corporation

20080177982 - Memory and accessing method thereof: The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of... Agent: Wpat, Pc

20080177983 - Selective suppression of register renaming: A register renaming unit 8 has mapping control circuitry 24 which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system 2. One example of circumstances which can be detected from the current state and in which mapping can be suppressed and... Agent: Nixon & Vanderhye, Pc

20080177985 - Condition code flag emulation for program code conversion: An emulator allows subject code written for a subject processor having subject processor registers and condition code flags to run in a non-compatible computing environment. The emulator identifies and records parameters of instructions in the subject code that affect status of the subject condition code flags. Then, when an instruction... Agent: Wilmerhale/boston

20080177984 - Suppressing register renaming for conditional instructions predicted as not executed: Within a data processing system 2 including a register renaming mechanism 8, 22, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known... Agent: Nixon & Vanderhye, Pc

20080177986 - Method and software for group data operations: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group... Agent: Mcdermott Will & Emery LLP

20080177988 - Partial load/store forward prediction: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080177987 - Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction: Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs... Agent: Qualcomm Incorporated

20080177989 - Defining memory indifferent trace handles: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.... Agent: Heslin Rothenberg Farley & Mesiti P.c.

20080177991 - Method and device for improving debug time of a display apparatus: A method and a device for improving debug time of a display apparatus are provided. The display apparatus includes an input signal connector for receiving an external input signal, an MCU, a bus and a plurality of units. The input signal connector is connected to the MCU via the bus,... Agent: Jianq Chyun Intellectual Property Office

20080177990 - Synthesized assertions in a self-correcting processor and applications thereof: The present invention provides one or more synthesized assertions in a self-correcting processor, and applications thereof. In an embodiment, a synthesized assertion detects a mismatch between actual processor behavior and specified or expected processor behavior. When unexpected processor behavior is encountered, the synthesized assertion alters operation of the processor and... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080177992 - Segmented pipeline flushing for mispredicted branches: A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target... Agent: Qualcomm Incorporated

20080177993 - System, method and program product for control of sequencing of data processing by different programs: A first piping application is defined by combining first and second stages of programming with a first sequence control program and specifying to the first sequence control program a first piping command. The second stage is a function to send data to a shared queue. The first piping command identifies... Agent: Ibm Corporation

20080172546 - Digital signal processor: A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a... Agent: Quintero Law Office, PC

20080172547 - Reusing a buffer memory as a microcache for program instructions of a detected program loop: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector... Agent: Nixon & Vanderhye, PC

20080172549 - Method and apparatus for counting instructions during speculative execution: One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080172548 - Method and apparatus for measuring performance during speculative execution: One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080172550 - Method and circuit implementation for multiple-word transfer into/from memory subsystems: A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask... Agent: Jianq Chyun Intellectual Property Office

20080172551 - Operation verification method for verifying operations of a processor: To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point addition instruction to be verified is created, and operands used for this addition are created at random. The floating-point addition instruction thus created... Agent: Staas & Halsey LLP

20080172552 - Method for the selective and collective transmission of messages in a tmn network: The invention relates to a method and to a dvice for the selective and/or time-delayed and collective transmission of messages in a TMN system that is managed according to ITU-T recommendations. To this end, a MassEventDiscriminator is defined as the object class and a MassEventPreprocessor, using the MassEventDiscriminator, transmits only... Agent: Bell, Boyd & Lloyd, LLP

20080168255 - Method and apparatus for self-healing symmetric multi-processor system interconnects: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080168256 - Modular distributive arithmetic logic unit: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte... Agent: Bever, Hoffman & Harms, LLP

20080168257 - Interface assembly for coupling a host to multiple storage devices: In some embodiments, a storage processor interface assembly includes a circuit board supporting a storage processor, first and second standard compliant power connectors, and first, second, and third standard compliant data connectors. The second power connector and the second data connector are positioned such that they may mate with corresponding... Agent: Silicon / Blakely Blakely Sokoloff Taylor & Zafman

20080168258 - Method and apparatus for selecting the architecture level to which a processor appears to conform: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the... Agent: Dillon & Yudell LLP

20080168259 - Descriptor prefetch mechanism for high latency and out of order dma device: A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080168260 - Symbolic execution of instructions on in-order processors: A method is provided for processing instructions by a processor, in which instructions are queued in an instruction pipeline in a queued order. A first instruction is identified from the queued instructions in the instruction pipeline, the first instruction being identified as having a dependency which is satisfiable within a... Agent: Ibm Corporation, T.j. Watson Research Center

20080168261 - Queue design system supporting dependency checking and issue for simd instructions within a general purpose processor: A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a... Agent: Ibm Corporation (cs) C/o Carr LLP

20080168262 - Methods and apparatus for software control of a non-functional operation on memory: In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the... Agent: Matthew C. Zehrer, Agent IBM Corporation, Dept. 917

20080168263 - Branch target buffer and method of use: A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line... Agent: Volentine & Whitt PLLC

20080162870 - Virtual cluster architecture and method: Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch, and an inter-cluster communication mechanism. This invention uses a way of time sharing or time multiplexing to alternatively execute a single... Agent: Lin & Associates Intellectual Property, Inc.

20080162871 - Multi-source dual-port linked list purger: Disclosed is a circuit for simultaneously searching two ends of a vector. The circuit comprises at least one input for receiving a vector of head pointers. A first input of a memory latch receives the vector of head pointers. An input of a first priority decoder receives the vector of... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20080162872 - Data processing system, method and interconnect fabric supporting high bandwidth communication between nodes: A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each... Agent: Dillon & Yudell LLP

20080162873 - Heterogeneous multiprocessing: In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security (SEC), pre-EFI initialization (PEI), and then driver execution environment (DXE) phases are executed in parallel on multiple compute nodes (sockets) of a platform.... Agent: Intel Corporation C/o Intellevate, Llc

20080162874 - Parallel data processing apparatus: A data transfer controller for controlling transfer of data items in a data processing system comprising a single instruction multiple data (SIMD) array of processing elements is disclosed. The controller comprises a transfer controller operable to control transfer of data to and/or from an internal memory unit of a processing... Agent: Glenn Patent Group

20080162875 - Parallel data processing apparatus: A method of controlling access to memory by a processing element in a plurality of processing elements arranged in a single instruction multiple data (SIMD) processing array is disclosed. Each processing element includes an internal memory unit, and a register file. The method comprises retrieving an address value from the... Agent: Glenn Patent Group

20080162876 - dedicated hardware processor for structured query language (sql) transactions: The present solution can include a SQL coprocessor. The SQL coprocessor can comprise silicon-based logic within which a set of machine-readable instructions that are associated with one or more silicon-based components of a database architecture can be implemented. A silicon-based component can include a protocol interface component, a SQL parsing... Agent: Patents On Demand, P.a.

20080162877 - Non-homogeneous multi-processor system with shared memory: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080162878 - Multi-socket boot: In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security (SEC), pre-EFI initialization (PEI), and then driver execution environment (DXE) phases are executed in parallel on multiple compute nodes (sockets) of a platform.... Agent: Intel Corporation C/o Intellevate, Llc

20080162879 - Methods and apparatuses for aligning and/or executing instructions: In some embodiments, a method includes receiving a sequence of instructions in a processing system, determining whether an instruction in the sequence is a type to be aligned, and if the instruction is a type to be aligned, aligning the instruction. In some embodiments, a method includes receiving an instruction... Agent: Buckley, Maschoff & Talwalkar Llc

20080162880 - System and method for translating non-native instructions to native instructions for processing on a host processor: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080162881 - Mechanism for irrevocable transactions: A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner... Agent: Intel Corporation C/o Intellevate, Llc

20080162882 - System and apparatus for group data operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Mcdermott Will & Emery LLP

20080162883 - Structure for a single shared instruction predecoder for supporting multiple processors: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162884 - Computer processing system employing an instruction schedule cache: A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename... Agent: Cantor Colburn LLP-ibm Yorktown

20080162886 - Handling precompiled binaries in a hardware accelerated software transactional memory system: A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access... Agent: Intel Corporation C/o Intellevate, Llc

20080162885 - Mechanism for software transactional memory commit/abort in unmanaged runtime environment: A method and apparatus for ensuring integrity of transaction exit functions is herein described. Dead local data in a transaction is prevented from overwriting local variables associated with a transaction exit function. In a write-buffering Software Transactional Memory (STM) system, a commit function is associated with a private stack to... Agent: Intel Corporation C/o Intellevate, Llc

20080162887 - System for generating effective address: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080162888 - Differential comparison system and method: A method and computer program product for monitoring the chronological order in which one or more portions of a first instance of a computer program are executed, thus generating a first data file. The chronological order in which one or more portions of a second instance of the computer program... Agent: Holland & Knight

20080162889 - Method and apparatus for implementing efficient data dependence tracking for multiprocessor architectures: A system for tracking memory dependencies includes a speculative thread management unit, which uses a bit vector to record and encode addresses of memory access. The speculative thread management unit includes a hashing unit that partitions the addresses into a load hash set and a store hash set, a load... Agent: Mcginn Intellectual Property Law Group, Pllc

20080162890 - Computer processing system employing an instruction reorder buffer: A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after... Agent: Cantor Colburn LLP-ibm Yorktown

20080162894 - structure for a cascaded delayed execution pipeline: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided for improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162895 - Design structure for a mechanism to minimize unscheduled d-cache miss pipeline stalls: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for minimizing unscheduled D-cache miss pipeline stalls is provided. The design structure includes an integrated circuit device, which includes a cascaded delayed execution pipeline unit having two or more execution pipelines that begin... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162891 - Extensible microcomputer architecture: Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path... Agent: Microsoft Corporation

20080162892 - Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium: According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and... Agent: Foley And Lardner LLP Suite 500

20080162893 - Method and hardware apparatus for implementing frame alteration commands: A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recognition result of a received packet. A frame alteration instruction stream is generated... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080162896 - Apparatus and method for generating packed sum of absolute differences: A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed differences: determining whether the borrow bit indicates the packed difference is... Agent: Huffman Law Group, P.c.

20080162897 - Binary logic unit and method to operate a binary logic unit: A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va,... Agent: Ibm Corporation Rochester Ip Law Dept. 917

20080162899 - Compressed data transfer apparatus and method for transferring compressed data: According to an embodiment, a compressed data transfer apparatus includes: a data size calculation unit that calculates a data size to be transferred to a decoding apparatus for a time period corresponding to a difference between a first decoding delay time for which a last decode unit data in a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080162898 - Register map unit supporting mapping of multiple register specifier classes: Embodiments of this invention relate to sharing resources on a semiconductor between multiple functional units to reduce the number of register rename mappers and particularly to providing a way to share a CAM mapper between two distinct physical register files. In one embodiment the physical register files correspond to architectural... Agent: Cantor Colburn LLP-ibm Yorktown

20080162900 - System, method and apparatus for observing a control device: This aspect of the current invention is carried out for example in that a monitoring service is installed on the control device for execution by way of the micro-controller, that upon the control device is provided at least one separate trace address area within the address space with at least... Agent: Chadbourne & Parke LLP

20080162901 - Computer multiple operation system switching method: The present invention discloses a computer multi-OS switching method, in which a data exchange region for storing OS running environment information is provided, wherein the method comprises: A. saving running information of computer hardware devices in a random access memory (RAM) by the computer after receiving a command for switching... Agent: Westman Champlin & Kelly, P.a.

20080162902 - Delayed branch decision in quadrature decomposition with m-searching: A QRD-M decomposition includes a first and a sequential second stage, at least. In the first stage, M branches are selected from among more than M branches entering the first stage as survive branches from which multiple decompositions are calculated. In the second stage, more than M branches are selected... Agent: Harrington & Smith, Pc

20080162903 - Information processing apparatus: There is provided an information processing apparatus characterized by including: an instruction cache memory storing an instruction; a first adder adding a program counter relative branch target address in an inputted branch instruction and a program counter value, and outputting an absolute branch target address; and a write circuit converting... Agent: Staas & Halsey LLP

20080162904 - Apparatus for selecting an instruction thread for processing in a multi-thread processor: The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that... Agent: Ibm Corporation (shc) C/o The Culbertson Group, P.c.

20080162905 - Design structure for double-width instruction queue for instruction execution: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally comprises a processor, which generally comprises a cache, a dual instruction queue comprising a first queue and a second queue, an execution unit, and circuitry. The circuitry... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162906 - Hiding memory latency: An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080162907 - Structure for self prefetching l2 cache mechanism for instruction lines: A design structure for prefetching instruction lines is provided. The design structure is embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design. The design structure comprises a processor. The processor generally comprises a level 2 cache, a level 1 cache configured to receive instruction lines... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162908 - structure for early conditional branch resolution: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure comprises a processor. The processor comprises a cache, an execution unit, and circuitry. The circuitry is configured to receive a branch instruction from the cache to be executed... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080162909 - Compilation and runtime information generation and optimization: To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency... Agent: Scully, Scott, Murphy & Presser, P.c.

20080162910 - Asynchronous control transfer: Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed to obtain the address of a yield service routine. Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate, Llc

20080162911 - High performance renormalization for binary arithmetic video coding: Various embodiments for high performance renormalization for video encoding are described. In one or more embodiments, renormalization may involve detecting a leading number of ‘0’s in a range value of an input stream of symbols, a run of ‘1’s in an offset value of the input stream of symbols, and... Agent: Kacvinsky Llc C/o Intellevate