Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 06/08

20080155230 - Method and system for providing simultaneous transcoding of multi-media data: A method and system for providing simultaneous transcoding of multi-media data are disclosed. For example, the method receives multi-media data in a first format. In turn, the method transmits the multimedia data to an output device, while simultaneously transcoding the multi-media data into at least one alternate format.... Agent: Motorola, Inc. Law Department

20080155231 - Method and data processing system for processor-to-processor communication in a clustered multi-processor system: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network... Agent: Dillon & Yudell LLP

20080155232 - Sharing a data buffer: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or... Agent: Fish & Richardson P.c.

20080155233 - Apparatus for adjusting instruction thread priority in a multi-thread processor: Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between... Agent: Ibm Corporation (shc) C/o The Culbertson Group, P.c.

20080155234 - Thread starvation profiler: A profiler of a multithreaded process that determines whether a process is runnable but not running by determining whether a process is both waiting for the processor and also not waiting for other events such as I/O. Counters are maintained for each such process that is runnable but not running.... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.c.

20080155235 - Instructions capable of preventing incorrect usage of ucontext functions in a multi-process environment: An instruction capable of preventing incorrect usage of ucontext functions in a multi-process environment is disclosed. During an execution of a setcontext instruction, a determination is made whether or not a contextID of a context structure associated with a next context indicates that it is an original context of a... Agent: Dillon & Yudell, LLP

20080155236 - System and method for implementing a zero overhead loop: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080155237 - System and method for implementing and utilizing a zero overhead loop: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080155238 - Combining data processors that support and do not support register renaming: A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said... Agent: Nixon & Vanderhye, Pc

20080155239 - Automata based storage and execution of application logic in smart card like devices: A small intelligent device has a memory that stores a finite state automaton, an input/output interface that receives an input and provides an output, and a processor. The processor is arranged to receive the input and to traverse the finite state automaton stored in the memory in order to supply... Agent: Honeywell International Inc.

20080148009 - Processing system with interspersed processors and communication elements: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a... Agent: Jeffrey C. Hood Meyertons, Hood, Kivlin, Kowert & Goetzel Pc

20080148010 - Semiconductor integrated circuit: The system design is facilitated by eliminating the increase in data transfer volume of the whole system. In order to facilitate the system design, there are provided an operation unit array, a memory array, a data transfer circuit, and a switch circuit. There are also provided a configuration data management... Agent: Miles & Stockbridge Pc

20080148011 - Carry/borrow handling: The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary... Agent: Grossman, Tucker, Perreault & Pfleger, Pllc C/o Intellevate, Llc

20080148012 - Mathematical operation processing apparatus: A mathematical operation processing apparatus is disclosed by which the supply of an operand which is performed based on condition codes by a plurality of mathematical operations can be performed at a high speed. The mathematical operation processing apparatus includes a plurality of computing elements configured to perform different mathematical... Agent: Rader Fishman & Grauer Pllc

20080148013 - Rdma method for mpi_reduce/mpi_allreduce on large vectors: Methods, systems and computer programs for distributing a computing operation among a plurality of processes and for gathering results of the computing operation from the plurality of processes are described. An exemplary method includes the operations of pairing a plurality of processes such that each process has a maximum of... Agent: International Business Machines Corporation

20080148014 - Method and system for providing a response to a user instruction in accordance with a process specified in a high level service description language: A method, system, and computer program product for providing a response to a user instruction in accordance with a process specified in a high level service description language. A method in accordance with an embodiment of the present invention includes: receiving at a multimodal engine a user instruction using one... Agent: Hoffman, Warnick & D'alessandro Llc

20080148015 - Method for improving reliability of multi-core processor computer: In a system including a plurality of multi-core processors, a table for managing the processors and cores owned by the processors is provided and a single virtual server is formed by using cores owned by different processors when generating the virtual server. According to the number owned by processors, the... Agent: Mcdermott Will & Emery LLP

20080148016 - Multiprocessor system for continuing program execution upon detection of abnormality: A multiprocessor system includes a plurality of processors, wherein instruction codes of a program executed by the processors are stored in an internal memory of each of the processors, wherein one of the processors includes a program counter configured to indicate an address of a program instruction being executed in... Agent: Katten Muchin Rosenman LLP

20080148017 - Systems for executing load instructions that achieve sequential load consistency: A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache... Agent: Ibm Corporation (cs) C/o Carr LLP

20080148019 - Instruction set extension using 3-byte escape opcode: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the... Agent: Blakely Sokoloff Taylor & Zafman

20080148018 - Shift processing unit: The present invention is a technique to perform field operations. A shifter to shift an operand. A register stores the shifted operand. A shift post processor processes the shifted operand based on at least a control signal and an offset parameter.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080148020 - Low cost persistent instruction predecoded issue and dispatcher: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080148021 - High frequency stall design: An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080148022 - Marking registers as available for register renaming: The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for... Agent: Nixon & Vanderhye, Pc

20080148023 - Method and system for synchronous operation of an application by a purality of processing units: A method for effecting synchronized operation of an application by a plurality of processing units, each processing unit may include an application processing section coupled with an own data store and a communication section coupled for communications with other processing units, includes: (a) operating each processing unit to store data... Agent: Law Office Of Donald D. Mondul

20080148024 - Hardware accelerator: The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum... Agent: Grossman, Tucker, Perreault & Pfleger, Pllc C/o Intellevate, Llc

20080148025 - High performance raid-6 system architecture with pattern matching: An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are... Agent: Intel Corporation C/o Intellevate, Llc

20080148026 - Checkpoint efficiency using a confidence indicator: In one embodiment, a processor comprises a predictor, a checkpoint unit, and circuitry coupled to the checkpoint unit. The predictor is configured to predict an event that can occur during an execution of an instruction operation in the processor. Furthermore, the predictor is configured to provide a confidence indicator corresponding... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080148027 - Method and apparatus of power managment of processor: Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and... Agent: Pearl Cohen Zedek Latzer, LLP

20080148028 - Predicting branch instructions: A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of... Agent: Nixon & Vanderhye, Pc

20080148029 - Data processing apparatus and method for converting data values between endian formats: A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided within the data processing apparatus for receiving a block of data containing at least one data value, and for converting each data value in... Agent: Nixon & Vanderhye, Pc

20080140989 - Multiprocessor architecture with hierarchical processor organization: A computing system is provided that has a multiprocessor architecture. The processors are hierarchically organized so that one or more slave processors at a senior hierarchical level provide tasks to one or more slave processors at a junior hierarchical level. Further, the slave processors at the junior hierarchical level will... Agent: Banner & Witcoff, Ltd.

20080140990 - Accelerator, information processing apparatus and information processing method: Systems and methods for accelerators which may execute a program in conjunction with a PC are disclosed. In one embodiment, an accelerator includes a plurality of calculation units, each calculation unit operable to execute the program in parallel, an operation control unit configured to control an operation capability or a... Agent: Sprinkle Ip Law Group

20080140991 - Dynamic programmable intelligent search memory: Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory derived using randomly accessible dynamic memory circuits that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being... Agent: Dla Piper Us LLP

20080140992 - Performing endian conversion: A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB) instruction. An endian conversion is performed on the data that is moved into and moved out of... Agent: Intel/blakely

20080140994 - Data-parallel processing unit: A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more... Agent: Shemwell Mahamedi LLP

20080140993 - Fetch engine monitoring device and method thereof: In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence... Agent: Larson Newman Abel Polansky & White, LLP

20080140995 - Information processor and instruction fetch control method: In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem, provided is an information processor... Agent: Mcginn Intellectual Property Law Group, Pllc

20080140996 - Apparatus and methods for low-complexity instruction prefetch system: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the... Agent: Qualcomm Incorporated

20080140997 - Data processing system and method: Embodiments of the present invention relate to a data processing system and method for using metadata associated with data to be retrieved from storage to identify further data to be retrieve at least a portion of that further data from the storage in accordance with a prefetch policy.... Agent: Hewlett Packard Company

20080140998 - Integrated mechanism for suspension and deallocation of computational threads of execution in a processor: A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input... Agent: Huffman Law Group, P.c.

20080140999 - Programmable video signal processor for video compression and decompression: A data processing method with multiple issue multiple datapath architecture in a video signal processor (VSP) is provided. In the method, commands are received from the external signal processor. The received commands are routed to a plurality of separate command sequencers, an Input/output (IO) processor or a plurality of configure... Agent: J C Patents, Inc.

20080141000 - Intelligent smt thread hang detect taking into account shared resource contention/blocking: Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080141001 - Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system: A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central processing unit (CPU) and the stages of the pipelines. A master configuration register set is loaded with configuration parameters by the... Agent: Law Offices Of Ronald M Anderson

20080141004 - Apparatus and method for performing re-arrangement operations on data: An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has... Agent: Nixon & Vanderhye, Pc

20080141003 - Hybrid data object model: Computer implemented method, system and computer usable program code for processing a data object, for example, for searching for, creating or updating a data object. A computer implemented method for processing a data object includes receiving a request for the data object. A static portion and a dynamic portion for... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080141002 - Instruction pipeline monitoring device and method thereof: In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence... Agent: Larson Newman Abel Polansky & White, LLP

20080141005 - Method and apparatus for counting instruction execution and data accesses: A method, apparatus, and computer instructions in a data processing system for processing instructions. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled.... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080141006 - System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences: A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the... Agent: Dillon & Yudell LLP

20080141007 - Boolean processor: A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/output interfaces are operable for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality... Agent: Kilpatrick Stockton LLP

20080141009 - Communication apparatus: A processor transfers control information set for each connection from a second memory to a first memory, and updates the control information stored in the first memory in accordance with processing of the connection. The processor selects control information updated in the first memory, and transfers the selected control information... Agent: Morgan & Finnegan, L.l.p.

20080141008 - Execution engine monitoring device and method thereof: In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence... Agent: Larson Newman Abel Polansky & White, LLP

20080141010 - Data processing system and method supporting addition of a hardware component to a running system: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access,... Agent: Dillon & Yudell LLP

20080141011 - Selecting formats for multi-format instructions in binary translation of code from a hybrid source instruction set architecture to a unitary target instruction set architecture: A method, according to one aspect, may include estimating costs associated with translating a multi-format instruction of a source instruction set architecture to instructions of a target instruction set architecture by using a different format of the multi-format instruction for each of the costs, and selecting a format for the... Agent: Blakely Sokoloff Taylor & Zafman

20080141012 - Translation of simd instructions in a data processing system: A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon... Agent: Nixon & Vanderhye, Pc

20080141013 - Digital processor with control means for the execution of nested loops: A method and apparatus to control execution of nested loops is disclosed. The method and apparatus stores the loop level of a current loop in execution and uses this loop level to manage a data set provided for each loop. The data set for each loop includes a start address,... Agent: Schneck & Schneck

20080141014 - Load address dependency mechanism system and method in a high frequency, low power processor system: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a... Agent: Ibm Corporation (cs) C/o Carr LLP

20080133879 - Simd parallel processor with simd/sisd/row/column operation modes: Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required... Agent: Blakely Sokoloff Taylor & Zafman

20080133880 - Instruction controlled data processing device: The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction... Agent: Philips Intellectual Property & Standards

20080133881 - Array of processing elements with local registers: Specialized image processing circuitry is usually implemented in hardware in a massively parallel way as single instruction multiple data (SIMD) architectures. Known implementations suffer from the long and complicated connection paths between a processing element and the memory subsystem, and the resulting limitation of maximum operating frequency. An optimized architecture... Agent: Joseph J. Laks Thomson Licensing Llc

20080133882 - Wavescalar architecture having a wave order memory: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as... Agent: Law Offices Of Ronald M Anderson

20080133883 - Hierarchical store buffer: A hierarchical store buffer included in a hierarchical microprocessor includes a plurality of execution clusters. An embodiment of a hierarchical store buffer includes a first-level store buffer configured to receive data values to be written to a memory subsystem from the plurality of execution clusters and store the received data... Agent: Brake Hughes Bellermann LLP

20080133884 - Multiple network connections for multiple computers: A system and method for interconnecting multiple computers (M1, M2, . . . , Mn) via at least two independent communications ports (28, 38) are disclosed. Data is sent and received via a data protocol which identifies the sequence position of each data packet in a transmitted sequence of data... Agent: Perkins Coie LLP

20080133885 - Hierarchical multi-threading processor: A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each... Agent: Brake Hughes Bellermann LLP

20080133886 - Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches: A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080133887 - Data processing apparatus of high speed process using memory of low speed and low power consumption: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of... Agent: Mcdermott Will & Emery LLP

20080133888 - Data processor: The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical functions as an integrated whole of processors (CPU1 and CPU2)... Agent: Stanley P. Fisher Reed Smith LLP

20080133889 - Hierarchical instruction scheduler: A hierarchical instruction scheduler included in a hierarchical microprocessor comprising a plurality of execution clusters. In one embodiment, a hierarchical instruction scheduler comprises a first-level instruction scheduler configured to receive instructions for execution; store first operand status information for respective operands of the instructions; and dispatch the instructions to respective... Agent: Brake Hughes Bellermann LLP

20080133890 - Dynamic recalculation of resource vector at issue queue for steering of dependent instructions: A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared... Agent: Ibm Corporation (syl) C/o Synnestvedt & Lechner LLP

20080133891 - Data parallelism and parallel operations in stream processing: A stream processing platform that provides fast execution of stream processing applications within a safe runtime environment. The platform includes a stream compiler that converts a representation of a stream processing application into executable program modules for a safe environment. The platform allows users to specify aspects of the program... Agent: Wolf Greenfield & Sacks, P.c.

20080133893 - Hierarchical register file: A hierarchical register file included in a hierarchical microprocessor that includes a plurality of execution clusters. An embodiment of the a hierarchical register file includes a first-level register file including a plurality of mappable registers. where the first level register filed is configured to allocate the mappable registers to store... Agent: Brake Hughes Bellermann LLP

20080133892 - Methods and apparatus for initiating and resynchronizing multi-cycle simd instructions: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose... Agent: Priest & Goldstein Pllc

20080133894 - System and method for storing immediate data: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.... Agent: Trop Pruner & Hu, Pc

20080133895 - Floating point addition: Methods and apparatus to perform floating point addition are described. In one embodiment, a plurality of operands are formatted into a common format and combined (e.g., added or subtracted). Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate

20080133897 - Diagnostic apparatus and method: t

20080133896 - User-space return probes: A computer system is provided with memory divided by the operating system into kernel space and user space. A probe function is provided in a related user-space application to support dynamic insertion of instrumentation into the application. A breakpoint instruction is provided in an area of the process's user space... Agent: Lieberman & Brandsdorfer, Llc

20080133898 - Technique for context state management: A technique for managing context state information. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information. One embodiment includes at least one in-use bit vector to indicate status of the plurality of machine context information.... Agent: Blakely Sokoloff Taylor & Zafman

20080133899 - Context switching method, medium, and system for reconfigurable processors: A context switching method, medium, and system with a reconfigurable processor. The context switching system include a reconfigurable processor reconfiguring a program according to reconfiguration information and executing the reconfigured program, a central processing unit outputting a load command for sequentially loading reconfiguration information required for a plurality of tasks,... Agent: Staas & Halsey LLP

20080133900 - Machine learning performance analysis tool: In general, in one aspect, the disclosure describes a method that includes interrupting a program running on a processor. The active instruction that was interrupted is identified. Event counts since a previous interrupt are harvested.... Agent: Ryder Ip Law C/o Intellevate