Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 05/08

20080126743 - Reducing stalls in a processor pipeline: Systems and methods are disclosed herein for processing instructions in a processor pipeline to reduce the number of stalls therein. In an exemplary embodiment, a processor pipeline comprises a fetch stage configured to fetch instructions to be processed in the processor pipeline, a decode stage configured to decode the fetched... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080126744 - Method and apparatus for loading or storing multiple registers in a data processing system: A method for operating a data processing system includes providing an application binary interface (ABI) which determines a set of non-contiguous volatile registers and a set of non-volatile registers. The set of non-contiguous volatile registers includes a plurality of general purpose registers (GPRs) and a plurality of special purpose registers... Agent: Freescale Semiconductor, Inc. Law Department

20080126745 - Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080126746 - Network of single-word processors for searching predefined data in transmission packets and databases: The present invention related to monitoring internet traffic for illegal Intellectual Property transfers, viruses, criminal and other illegal activities. It also assists the Internet search engine providers in generating fast and accurate responses to Internet Recipient (IR) database queries. A massively parallel network of processing units residing within a single... Agent: Weiss & Moy PC

20080126747 - Methods and apparatus to implement high-performance computing: Apparatus and methods to implement high-performance computing are disclosed. An example method comprises executing a first operating system in a first partition to detect an arithmetic instruction, using an inter-partition bridge to notify a second partition of the arithmetic instruction, and processing the arithmetic instruction in the second partition with... Agent: Hanely Flight & Zimmerman, LLC

20080126748 - Multiple-core processor: A method, apparatus, and computer program product for using a multi-core integrated circuit to extend the reliability or operating life of an electronic device.... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080126751 - Scheduler hint method and system to improve network interface controller (nic) receive (rx) processing cache performance: Aspects of a scheduler hint method and system to improve network interface controller (NIC) receive (RX) processing cache performance are presented. Aspects of a system may include a NIC that enables generation of a processor selection bias value. The processor selection bias value may comprise hint data. A scheduler within... Agent: Mcandrews Held & Malloy, Ltd

20080126750 - System and method for aggregating core-cache clusters in order to produce multi-core processors: According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.... Agent: Intel/blakely

20080126749 - Using shared memory with an execute-in-place processor and a co-processor: The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in place to enable it... Agent: Amin, Turocy & Calvin, LLP

20080126752 - Dual-processor communication: A method for dual-processor communication. In one example embodiment, a method includes indicating to a master processor that data is available to transfer to the master processor; receiving a request for the data from the master processor over a storage-based channel; and sending the data to the master processor over... Agent: Workman Nydegger

20080126753 - Embedded system and operating method thereof: An embedded system and an operating method thereof are disclosed. The embedded system comprises a micro-processor and a co-processor. The co-processor can only process non-interruptible instructions. The micro-processor is powered by an operating system to control the embedded system. When a task requires execution, the micro-processor appoints the co-processor to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080126754 - Multiple-microcontroller pipeline instruction execution method: The present invention discloses a multiple-microcontroller pipeline instruction execution method, wherein the multiple-microcontroller includes a plurality of MCUs, the method comprising: fetching an instruction by a first MCU in a first instruction cycle, and fetching another instruction by a second MCU in a second instruction cycle immediately following the first... Agent: Tung & Associates

20080126757 - Cellular engine for a data processing system: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of... Agent: Haverstock & Owens LLP Attn: Thomas B. Haverstock

20080126756 - Data processing apparatus and data processing method: A data processing apparatus includes an operation processing unit and a data feature determining circuit. The operation processing unit is configured to sequentially perform preset operation processing on operation data in units of sub blocks to output an operation resultant data. Each of the operation data is divided into blocks,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080126755 - Methods and apparatus to form a transactional objective instruction construct from lock-based critical sections: Methods and an apparatus for forming a transaction object instruction construct are provided. An example method translates a source instruction construct to form a transactional objective instruction construct, executes the transactional objective instruction construct, intercepts an aborted transaction associated with the transactional objective instruction construct during execution, maintains a graph... Agent: Hanely Flight & Zimmerman, LLC

20080126758 - Digital signal processing apparatus and method for multiply-and-accumulate operation: A digital signal processing apparatus and method for MAC operation are disclosed. The DSP apparatus including: a first memory for storing a plurality of first operands; a second memory for storing a plurality of second operands; a MAC processor including a plurality of parallel MAC blocks disposed in parallel for... Agent: Ladas & Parry LLP

20080126759 - Register indirect access of program floating point registers by millicode: Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source... Agent: International Business Machines Corporation

20080126761 - Method and apparatus for scheduling optimization: A computer implemented method, data processing system, and a computer program product for improving the scheduling of system processes by the central processing unit. The process retrieves a set of profiling data from an executable object file for the application. The set of profiling data is associated with a given... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080126760 - Method for latest producer tracking in an out-of-order processor, and applications thereof: Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080126762 - Methods, systems, and apparatus for object invocation across protection domain boundaries: Methods, apparatus, systems, and computer program products for invoking remote process calls and facilitating inter-process communications in a protected memory system employ a kernel that supports remote invocation of objects by a system call. The system call may include an object identifier and a set of pointers to input and... Agent: Qualcomm Incorporated

20080126763 - Method of translating n to n instructions employing an enhanced extended translation facility: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080126766 - Securing microprocessors against information leakage and physical tampering: A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing... Agent: Fish & Richardson PC

20080126765 - Testing machine-readable instructions: Systems and techniques for testing machine-readable instructions. In one aspect, a method includes identifying a subroutine in a set of machine-readable instructions that can request a service from a service provider, modifying the identified subroutine to convey a description of a service request to a recorder, and storing the modified... Agent: Fish & Richardson, P.C.

20080126764 - Using transactional memory for precise exception handling in aggressive dynamic binary optimizations: Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a... Agent: Intel/blakely

20080126768 - Method and apparatus for aiding verification of circuit, and computer product: A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in the verification target circuit for each type of processing for each command executable by the verification target circuit. Thus, implementation description classification information can... Agent: Staas & Halsey LLP

20080126767 - Method and apparatus for obtaining stack traceback data for multiple computing nodes of a massively parallel computer system: A data collector for a massively parallel computer system obtains call-return stack traceback data for multiple nodes by retrieving partial call-return stack traceback data from each node, grouping the nodes in subsets according to the partial traceback data, and obtaining further call-return stack traceback data from a representative node or... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080126769 - Data processing with reconfigurable registers: A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion... Agent: Freescale Semiconductor, Inc. Law Department

20080126770 - Methods and apparatus for recognizing a subroutine call: An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the next sequential address after the non-sequential change in... Agent: Qualcomm Incorporated

20080126771 - Branch target extension for an instruction cache: An instruction cache (I-Cache) for a processor is configured to include a Branch Target Extension associated with each Instruction Sector. When an Instruction Sector is fetched, the Branch Target Extension is simultaneously fetched. If the Instruction Sector has a branch instruction that is predicted taken, then the branch target address... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20080120489 - Scalable multi-threaded sequencing/synchronizing processor architecture: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.... Agent: Texas Instruments Incorporated

20080120490 - Lock-free state merging in parallelized constraint satisfaction problem solvers: Solver state merging in parallel constraint satisfaction problem (CSP) solvers. Solver state during processing of a computational thread of parallel CSP solvers is represented as a set of support graphs. The support graphs are merged in a pairwise fashion, yielding a new conflict-free graph. The merge process is free of... Agent: Microsoft Corporation

20080120491 - Method and apparatus for retrieving application-specific code using memory access capabilities of a host processor: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one... Agent: Coats & Bennett, Pllc

20080120492 - Hardware flow control monitor: Systems for detecting unexpected program flow may include a hardware program flow monitor to generate an interrupt signal if a software program flow value does not match an incrementally updated hardware value when a processor executes a program flow check instruction. In some examples, a program of instructions may include... Agent: Fish & Richardson P.c.

20080120493 - Profiler for optimizing processor architecture and application: A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises... Agent: Sughrue Mion, Pllc

20080120494 - Methods and apparatus for a bit rake instruction: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing... Agent: Peter H. Priest

20080120495 - System and method of automated function activation for electronic devices: A system and method of storing a default function from among possible functions to be executed by a device, and executing the default function after a pre-defined interval, if during the interval a user does not respond to a notification of the upcoming execution of the default function, through the... Agent: Pearl Cohen Zedek Latzer, LLP

20080120496 - Data processing system, processor and method of data processing having improved branch target address cache: A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch... Agent: Dillon & Yudell LLP

20080114964 - Apparatus and method for cache maintenance: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache... Agent: Ibm Corporation

20080114965 - Buckets of commands in a multiprocessor-based verification environment: The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080114966 - Determining register availability for register renaming: A data processing apparatus 2 supports out-of-order processing register renaming using a renaming stage 8. A set of physical registers 16 is mapped to architectural registers. Available-register identifying logic 26 is used to identify which physical registers 16 are available for use by the renaming stage 8. The available-register identifying... Agent: Nixon & Vanderhye, Pc

20080114967 - Semiconductor integrated circuit device: There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of... Agent: Miles & Stockbridge Pc

20080114969 - Instructions for efficiently accessing unaligned partial vectors: One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the load-swapped-partial instruction specifies a source address in a memory, which is possibly an unaligned... Agent: Apple Computer, Inc. C/o Park, Vaughan & Fleming LLP

20080114968 - Instructions for efficiently accessing unaligned vectors: One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector from a naturally-aligned memory region encompassing the source address, and in doing so... Agent: Apple Computer, Inc. C/o Park, Vaughan & Fleming LLP

20080114970 - Processor supporting vector mode execution: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether,... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080114971 - Branch history table for debug: A computer implemented method, apparatus, and computer program product for preserving branch history data. The process creates a branch history table in a buffer. The process saves an address for each executed branch instruction that occurs during execution of code in the branch history table to form branch history data.... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080114972 - Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a... Agent: Qualcomm Incorporated

20080114973 - Dynamic hardware multithreading and partitioned hardware multithreading: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware... Agent: Hewlett Packard Company

20080114974 - Reconfigurable image processor and the application architecture thereof: A reconfigurable image processor for image processing includes an arithmetic module, a first memory unit, a bus control module and a connecting module. By setting different configurations or configuring connections among arithmetic units via the connecting module, the operations of arithmetic units are reconfigured to include different functions. The present... Agent: Birch Stewart Kolasch & Birch

20080114975 - Method and processing system for nested flow control utilizing predicate register and branch register: A method for nested flow control is disclosed. The method includes providing a predicate register and a branch register; receiving a plurality of instructions including flow control instructions; storing a depth level with the branch register each time a flow control instruction is fetched or decoded or executed; setting the... Agent: North America Intellectual Property Corporation

20080109633 - Program processing device and program processing method: A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out the program, and a data acquiring circuit connected to an external program processing device, for acquiring the program from... Agent: Cantor Colburn, LLP

20080109635 - General purpose array processing: General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and operations performed may be controlled based on opcodes. Processors may be shared, scalable, and configured to... Agent: Qualcomm Incorporated

20080109637 - Systems and methods for reconfigurably multiprocessing: A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.... Agent: Burns & Levinson, LLP

20080109639 - Execution of instructions within a data processing apparatus having a plurality of processing units: A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units... Agent: Nixon & Vanderhye, Pc

20080109634 - Credit-based activity regulation within a microprocessor: A technique to control power consumption within a microprocessor. More particularly, embodiments of the invention relate to a technique to control power and performance within one or more microprocessors by enforcing a credit-based instruction execution rate algorithm.... Agent: Trop Pruner & Hu, Pc

20080109636 - Launching a secure kernel in a multiprocessor system: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted... Agent: Trop Pruner & Hu, Pc

20080109638 - Launching a secure kernel in a multiprocessor system: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted... Agent: Trop Pruner & Hu, Pc

20080109640 - Method for changing a thread priority in a simultaneous multithread processor: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.c.

20080109641 - Automatic and systematic detection of race conditions and atomicity violations: A library or application is selected comprising one or more functions or methods. An interesting subset of the functions or methods is created. A plurality of multi-threaded test cases are generated from the subset of interesting functions or methods, with each test case comprising a unique pair or triple of... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080109642 - Monitor processor authentication key for critical data: A command generating and monitoring system includes a command processor configured to determine a command data set from a command input. A monitoring processor is coupled to the command processor and is configured to generate an authentication key by comparing the command data set received from the command processor to... Agent: Honeywell International Inc.

20080109643 - File processing device, file transmission device, and corresponding methods: Upon receiving a plurality of image files transmitted from a portable telephone 80, a multifunction printer 10 stores, of the image files received this time, the file name of an image file with no data loss into a RAM 76, and controls a printer unit 20 so that print processing... Agent: Edwards Angell Palmer & Dodge LLP

20080109644 - System and method for using a working global history register: A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline... Agent: Qualcomm Incorporated

20080109645 - Data processing apparatus for loop structure and method thereof: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs... Agent: Jianq Chyun Intellectual Property Office

20080109646 - Data processing apparatus for loop structure and method thereof: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs... Agent: Jianq Chyun Intellectual Property Office

20080104366 - Semiconductor chip: Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace at least one processing apparatus.... Agent: Rader Fishman & Grauer PLLC

20080104367 - Collective network for computer structures: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect... Agent: Scully, Scott, Murphy & Presser, P.C.

20080104368 - Storage element having data protection functionality: A storage element has data protection functionality for receiving a data-writing and a data-reading from a functional module. The storage element comprises a storage unit that has a memory region with a predetermined capacity for storing the data and stores the data written by the functional module, a data amount... Agent: Staas & Halsey LLP

20080104365 - Configurable processor design apparatus and design method, library optimization method, processor, and fabrication method for semiconductor device including processor: A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080104369 - Network interface card for use in parallel computing systems: A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises... Agent: Koestner Bertani LLP

20080104370 - Risc type of cpu and compiler to produce object program executed by the same: A RISC type of CPU is provided to execute an object program in which a stack area is used. The CPU is configured to have a return instruction based on an operand at which an open size is specified and to perform the return instruction when the stack area is... Agent: Harness, Dickey & Pierce, P.L.C

20080104371 - Method and system using hardware assistance for continuance of trap mode during or after interruption sequences: A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such as aborts, faults, interrupts, and traps. A set of processor fields are used to indicate whether or not one or more trap modes... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104372 - Method, apparatus and computer program for executing a program: There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined typical return values. For each predefined return value,... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104373 - Scheduling technique for software pipelining: An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in... Agent: Ibm Corp. (wsm) C/o Winstead Sechrest & Minick P.C.

20080104374 - Hardware sorter: A hardware sorter comprises a comparator matrix (104) for checking if each number in an unsorted array input (102) is at least equal to each other number, a set of column summers (108) for counting the number of numbers that each number is at least equal to, a decoder array... Agent: Motorola, Inc.

20080104375 - Programmable processor and method with wide operations: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP

20080104376 - Method and apparatus for performing group instructions: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080104377 - Method and system of overload control in packetized communication networks: In a method for processor overload control in a wireless or other network, a processor occupancy level (“PO”) of a network processing unit is monitored and compared to a target PO. If the measured PO exceeds the target PO, one or more network load sources are controlled to reduce the... Agent: Mccormick, Paulding & Huber LLP