Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 04/08

20080098200 - Two dimensional addressing of a matrix-vector register array: A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2,... Agent: Schmeiser, Olsen & Watts

20080098201 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.... Agent: Glenn Patent Group

20080098203 - Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry havingf fixed, application specific computational elements: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC... Agent: Nixon Peabody, LLP

20080098202 - Coupling a general purpose processor to an application specific instruction set processor: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP... Agent: Louis Paul Herzberg

20080098205 - Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations: Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at... Agent: The Nath Law Group

20080098204 - Method and apparatus for improving the efficiency of a processor instruction pipeline: A system and method are disclosed which may include providing a processor instruction pipeline having a main line and a branch line; executing at least one wait cycle for at least one wait instruction in said pipeline; and advancing at least selected instructions, that are initially located subsequent to at... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080098206 - Plotting device and plotting method: A reference address generator receives UV coordinate values from a shader, converts the value into a reference address for referring to a texture, and refers to a texture map or an instruction map stored in a texture memory based upon the reference address. The value referred to by the texture... Agent: Katten Muchin Rosenman LLP

20080098207 - Analyzing diagnostic data generated by multiple threads within an instruction stream: A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering... Agent: Nixon & Vanderhye, PC

20080098208 - Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems: A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately... Agent: Nixon & Vanderhye, PC

20080091917 - Apparatus and method for directing micro architectural memory region accesses: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may... Agent: Trop, Pruner & Hu, P.C.

20080091919 - Multi-channel multi-media integrated circuit and method thereof: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted... Agent: Tung & Associates Suite 120

20080091918 - Method and data processing system for microprocessor communication in a cluster-based multi-processor system: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each... Agent: Bracewell & Patterson, L.L.P.

20080091920 - Transferring data between registers in a risc microprocessor architecture: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A... Agent: Henneman & Associates, PLC

20080091921 - Data prefetching in a microprocessing environment: Systems and methods for prefetching data in a microprocessor environment are provided. The method comprises decoding a first instruction; determining if the first instruction comprises both a load instruction and embedded prefetch data; processing the load instruction; and processing the prefetch data, in response to determining that the first instruction... Agent: Stephen C. Kaufman IBM Corporation

20080091922 - Data stream prefetching in a microprocessor: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch... Agent: Ibm Corporation (dwl) C/o Lally & Lally, L.L.P.

20080091923 - Register-based instruction optimization for facilitating efficient emulation of an instruction stream: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080091924 - Vector processor and system for vector processing: An embodiment of a vector processor includes a vector control and distribution unit and lanes. In operation, the vector control and distribution unit receives vector instructions, decomposes the vector instructions into vector element operations, and forwards the vector element operations for execution. Each lane proceeds to execute vector element operations... Agent: Hewlett Packard Company

20080091925 - Method and software for group floating-point arithmetic operations: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group... Agent: Mcdermott Will & Emery LLP

20080091926 - Optimization of a target program: A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information processing apparatus that includes an output device and a computer readable storage medium storing the program code. At... Agent: Schmeiser, Olsen & Watts

20080091927 - Method and device for a switchover in a computer system having at least two processing units: A method and device for switching over in a computer system having at least two processing units, a switchover means and a compare means, switching over taking place between at least two operating modes, and a first operating mode corresponding to a compare mode, and a second operating mode corresponding... Agent: Kenyon & Kenyon LLP

20080091928 - Branch lookahead prefetch for microprocessors: A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and... Agent: Ibm Corporation (jvm)

20080086621 - Command supply device: A command supply device is provided that efficiently supplies a command sequence that forms a loop. The command supply device includes a loop command buffer in which the command supply device accumulates a first partial command sequence that is a head part of a first command sequence repeatedly supplied to... Agent: Greenblum & Bernstein, P.L.C

20080086622 - Replay reduction for power saving: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080086623 - Strongly-ordered processor with early store retirement: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080086625 - Apparatus and method for updating the function of monitor: The present invention provides an apparatus for updating the function of a monitor and the method thereof. The method comprises: coupling a scale controller and a memory device of at least a monitor to a microcontroller; controlling the microcontroller to send a programming activation signal in a first signal format... Agent: North America Intellectual Property Corporation

20080086624 - Latch to block short path violation: An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10′, 10″ and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a... Agent: Nixon & Vanderhye, Pc

20080086626 - Inter-processor communication method: Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to relinquish control over at least one of the microprocessor's internal registers. The microprocessor may then signal a communication interface that collects data from external sources. The communication interface takes... Agent: Ropes & Gray LLP Patent Docketing 39/41

20080086627 - Methods and apparatus to analyze computer software: Methods and apparatus to analyze computer software are disclosed. The disclosed methods and apparatus may be used to verify and validate computer software. An example method includes receiving from a software test engine a definition of a graphical user interface associated with an application, receiving a user input indicating a... Agent: Hanley, Flight & Zimmerman, Llc

20080082783 - Dual independent and shared resource vector execution units with shared register file: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080082784 - Area optimized full vector width vector cross product: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080082785 - Vector completion mask handling: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for... Agent: Caven & Aghevli C/o Intellevate

20080082786 - Super-scalable, continuous flow instant logic™ binary circuitry actively structured by code-generated pass transistor interconnects: A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would... Agent: William S. Lovell

20080082787 - Delay circuit and processor: A delay circuit that can prevent an increase in the scale of circuits. A data delay section included in the delay circuit delays input data by a plurality of data delay elements. A validity information delay section included in the delay circuit delays input validity information which indicates that the... Agent: Arent Fox LLP

20080082788 - Pointer-based instruction queue design for out-of-order processors: A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access memory, a mapping table, and a multiple wake-up table. Instructions allocated to the instruction queue are identified by association with a physical... Agent: Shimokaji & Associates, P.C.

20080082789 - Interrupt handling: A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a... Agent: Schwabe, Williamson & Wyatt, P.C.

20080082790 - Memory controller for sparse data computation system and method therefor: An accelerator system supplements standard computer memory management units specifically in the case of sparse data. The accelerator processes requests for data from an analysis application running on the processor system by pre-fetching a subset of the irregularly ordered data and forming that data into a dense, sequentially-ordered array, which... Agent: Houston Eliseeva

20080082791 - Providing temporary storage for contents of configuration registers: In one embodiment, the present invention includes a method for assigning a first identifier to a first instruction that is to write control information into a configuration register, assigning the first identifier to a second instruction that is to read the control information written by the first instruction, and storing... Agent: Trop Pruner & Hu, PC

20080082792 - Register renaming in a data processing system: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further... Agent: Nixon & Vanderhye, PC

20080082793 - Detection and prevention of write-after-write hazards, and applications thereof: Apparatuses, systems, and methods for detecting and preventing write-after-write hazards, and applications thereof. In an embodiment, a load/store queue of a processor stores a first register destination value associated with a graduated load instruction. A graduation unit of the processor broadcasts a second register destination value associated with a graduating... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080082794 - Load/store unit for a processor, and applications thereof: A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080082795 - Twice issued conditional move instruction, and applications thereof: A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080082796 - Managing multiple threads in a single pipeline: In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue... Agent: Trop Pruner & Hu, PC

20080082797 - Configurable single instruction multiple data unit: Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of processing elements (PEs) and to perform instruction variances by the PEs. A CSIMD instruction is... Agent: Troutman Sanders LLP

20080082798 - Flexible microprocessor register file: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A... Agent: Creative/3dlabs/groover

20080082799 - Processing architectures with typed instruction sets: An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of... Agent: Creative/3dlabs/groover

20080082800 - Data processor for modifying and executing operation of instruction code: A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD instruction is placed in the right container. When the instruction decode unit decodes these instructions,... Agent: Buchanan, Ingersoll & Rooney PC

20080082801 - Apparatus and method for tracing instructions with simplified instruction state descriptors: A method of tracing processor instructions includes characterizing processor state changes in accordance with simplified instruction state descriptors. The simplified instruction state descriptors are then traced with processor instructions, but processor data is not traced.... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20080082802 - Microcomputer debugging system: A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the plurality of debug modes, and is allowed to shift to the interruption program during the debugging operation in another... Agent: Mcdermott Will & Emery LLP

20080082803 - Saving/restoring task state data from/to device controller host interface upon command from host processor to handle task interruptions: A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher... Agent: Epson Research And Development Inc Intellectual Property Dept

20080082804 - Method and apparatus for enabling optimistic program execution: A system that reduces overly optimistic program execution. During operation, the system encounters a bounded-execution block while executing a program, wherein the bounded execution block includes a primary path and a secondary path. Next, the system executes the bounded execution block. After executing the bounded execution block, the system determines... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080082805 - Automated synthesis apparatus and method: Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition... Agent: Sughrue Mion, PLLC

20080082806 - Cache controller, microprocessor system, and storage device: A cache controller prefetches instruction code from a memory and stores the instruction code in a cache. The cache controller comprises an address output section for, when an instruction fetch address from a processor is matched with a comparative address, outputting a prefetch address corresponding to the comparative address, and... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20080082807 - Effective use of a bht in processor having variable length instruction set execution modes: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table... Agent: Qualcomm Incorporated