Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 03/08

20080077768 - Merge operations based on simd instructions: A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge... Agent: Lieberman & Brandsdorfer, LLC

20080077769 - Apparatus for efficient lfsr in a simd processor: The apparatus provides for efficient implementation of multiple-bit leap-forward LFSR calculation in a SIMD processor. This provides an accelerated and programmable way to implement LFSR calculations in a SIMD processor. Conditional vector exclusive-OR accumulation is used by manipulating the leap-forward matrix, whereby one conditional vector exclusive-OR operation is performed for... Agent: Sawyer Law Group LLP

20080077770 - Method and apparatus for timing and event processing in wireless systems: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for... Agent: Wolf Greenfield & Sacks, P.C.

20080077771 - Long instruction word controlling plural independent processor operations: This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section... Agent: Robert D. Marshall, Jr. Texas Instruments Incorporated

20080077772 - Method and apparatus for performing select operations: A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand.... Agent: Blakely Sokoloff Taylor & Zafman

20080077773 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent: Caven & Aghevli C/o Intellevate

20080077774 - Hierarchical parallelism for system initialization: A technique includes using multiple processing cores of a semiconductor package to perform functions directed to booting up a computer system.... Agent: Trop Pruner & Hu, PC

20080077775 - Efficient non-blocking k-compare-single-swap operation: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory... Agent: Robert C. Kowert Meyertons, Hood, Kivlin, Kowert & Goetzel, P. C.

20080077776 - Load lookahead prefetch for microprocessors: The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080077778 - Method and apparatus for register renaming in a microprocessor: Register renaming as contemplated by this invention allows processor hardware to use a larger set of registers than the architected registers visible to the compiler. This larger set of registers is called the physical register file. Thus, dynamically renaming every compiler-suggested architected register to a microarchitecture-specific physical register, allows the... Agent: Ibm Corporation

20080077777 - Register renaming for instructions having unresolved condition codes: Register renaming logic is disclosed that is operable to map registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor... Agent: Nixon & Vanderhye, PC

20080077779 - Performing rounding operations responsive to an instruction: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit... Agent: Trop Pruner & Hu, PC

20080077780 - System and method for software debugging: The software debugging system provides a processor that is executing a software process, and the software process has a bug or other failure. A fast-response reporter circuit connects to a low level asset in the processor, such as a reorder buffer, commit buffer, or high speed data path. The fast... Agent: Willian J Kolegraff Law Office Of Bill Kolegraff

20080077781 - Methods and system for resolving simultaneous predicted branch instructions: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states.... Agent: Qualcomm Incorporated

20080077782 - Restoring a register renaming table within a processor following an exception: Control logic for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception is disclosed. The processor is operable to process a stream of instructions from an instruction set, the instruction set comprising exception instructions... Agent: Nixon & Vanderhye, PC

20080072010 - Data processor and methods thereof: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements.... Agent: Larson Newman Abel Polansky & White, LLP

20080072012 - System and method for processing user defined extended operation: An operation system and method of processing a user-defined extended operation are provided. The method includes using a software pipelining technology by enabling a processor to process a user-defined extended operation. An operation process system includes a plurality of functional units which are operable to process a primitive operation and... Agent: Sughrue Mion, PLLC

20080072013 - Microprocessor starting to execute a computer program at a predetermined interval: A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address updated every time when each... Agent: Posz Law Group, PLC

20080072011 - Simd type microprocessor: A SIMD type microprocessor that has two or more processor elements (PEs), and two or more computing units for every processor element (PE) is disclosed. According to the SIMD type microprocessor, each PE includes M arithmetic logic-operation circuits (M is a natural number 2 or greater), M registers for storing... Agent: Dickstein Shapiro LLP

20080072014 - Low power dual processor architecture for multi mode devices: A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor... Agent: Qualcomm Incorporated

20080072015 - Demand-based processing resource allocation: A technique to dynamically enable or disable a number of stacks within a processor based on demand. At least one embodiment includes logic to detect whether a stack is needed and to enable the stack in response thereto and to disable the stack if it no longer needed.... Agent: Caven & Aghevli C/o Intellevate

20080072016 - Entropy processor for decoding: A method for processing a variable length code comprising: determining a first address; decoding opcodes from the at least one table starting at a first address; in response to each of the opcodes: receiving a portion of a sequence of bits, the sequence of bits comprising a first variable length... Agent: Greenberg Traurig, LLP (sv)IPDocketing

20080072017 - Processing system having a plurality of processing units with program counters and related method for processing instructions in the processing system: A method for processing predetermined instructions in a processing system having a plurality of processing units includes providing a global program counter and setting a counter value of the global program counter as an instruction of the predetermined instructions is executed; assigning each processing unit a local program counter and... Agent: North America Intellectual Property Corporation

20080072018 - Data processing system, processor and method of data processing employing an improved instruction destination tag: A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective destination vector with each instruction. The destination vectors, which are of uniform size, identify which of a plurality of possible destinations for execution results... Agent: Dillon & Yudell LLP

20080072019 - Technique to clear bogus instructions from a processor pipeline: A technique to filter bogus instructions from a processor pipeline. At least one embodiment of the invention detects a bogus event, removes only instructions from the processor corresponding to the bogus event without affecting instructions not corresponding to the bogus event.... Agent: Caven & Aghevli C/o Intellevate

20080072021 - Floating point exception handling in a risc microprocessor architecture: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A... Agent: Henneman & Associates, PLC

20080072020 - Method and apparatus for programmable processor: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080072022 - Overlaping command committing method of dynamic cycle pipeline: The invention discloses an overlapping command committing method of dynamic cycle pipeline, for a chip having pipeline structure, the method comprising the following steps: reading the command from command buffer, decoding the command, judging whether operator is reasonable or not, if a illegal command, then deleting, otherwise preprocessing the operator... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080072023 - L driving method for driving program/instruction execution, and architecture and processor thereof: The invention relates to computer architecture technology in the computer field. More specifically, the invention relates to a novel driving method for driving computer program/instruction execution, and a computer processor architecture and computer processor using the method. As one of the features of the invention, even on condition that no... Agent: Cohen, Pontani, Lieberman & Pavane

20080072024 - Predicting instruction branches with bimodal, little global, big global, and loop (bggl) branch predictors: Methods and apparatus to perform efficient branch prediction operations are described. In one embodiment, branch prediction may be performed by utilizing a combination of a bimodal predictor, a plurality of global predictors, and a loop predictor. Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate

20080072025 - Software reconfigurable digital phase lock loop architecture: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner.... Agent: Texas Instruments Incorporated

20080065858 - System, method and apparatus to accelerate raid operations: A method according to one embodiment may include partitioning a plurality of core processors into a main partition comprising at least one processor core capable of executing a main operating system and an embedded partition comprising at least one different processor core configured to execute an embedded operating system. The... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Portfolio Ip

20080065859 - Processor architecture: A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution... Agent: Potomac Patent Group PLLC

20080065860 - Method and apparatus for performing improved data handling operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080065861 - Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a... Agent: Harrington & Smith, PC

20080065862 - Method and apparatus for performing data handling operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080065863 - Method and apparatus for data stream alignment support: One embodiment of the present method and apparatus for data stream alignment support includes retrieving a first input from a first register file, retrieving a second input from a second register file, the second register file being dedicated to a stream shift unit and performing the stream shift instruction in... Agent: Patterson & Sheridan LLP IBM Corporation

20080065866 - Apparatus and method for regulating bursty data in a signal processing pipeline: Apparatus and method for regulating data in a signal processing pipeline are disclosed. For example, an apparatus is disclosed that includes a first element operable to determine a time interval between a first plurality of data samples input to the signal processing pipeline, and calculate a sample spacing count value... Agent: Fogg & Powers LLC

20080065865 - In-use bits for efficient instruction fetch operations: Methods and apparatus to perform efficient instruction fetch operations are described. In an embodiment, one or more bits are utilized to determine when to modify an entry in a storage unit of a processor. Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate

20080065864 - Post-retire scheme for tracking tentative accesses during transactional execution: A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in... Agent: Intel Corporation C/o Intellevate, LLC

20080065867 - Multi-core processor control method: The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality... Agent: Bingham Mccutchen LLP

20080065868 - Software programmable hardware state machines: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080065869 - Computer system and control method thereof capable of changing performance mode using dedicated button: A computer system having a process running unit which runs processes of a plurality of programs; a user input unit through which a command of a user to select one of a plurality of performance modes is inputted; and a controller which controls the process running unit to run a... Agent: Stein, Mcewen & Bui, LLP

20080065870 - Information processing apparatus: An information processing apparatus characterized by having a memory interface with a buffer for reading and buffering an instruction stored in memory, an instruction decoder decoding a program counter relative branch instruction supplied from the above-mentioned memory interface, and extracting a program counter relative branch destination address in the above-mentioned... Agent: Staas & Halsey LLP

20080065871 - Operation synthesis system: An operation synthesis system includes a pipeline structure creating section for automatically creating, based on a state number assigned to a skip statement described in a high-level language in a transition to a pipeline operation and the number of cycles required to supply a pipeline with one loop designated by... Agent: Foley And Lardner LLP Suite 500

20080065872 - Methods and apparatus for preserving precise exceptions in code reordering by using control speculation: Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions... Agent: Hanley, Flight & Zimmerman, LLC

20080065873 - Dynamic livelock resolution with variable delay memory access queue: A method for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the... Agent: Dillon & Yudell LLP

20080059763 - System and method for fine-grain instruction parallelism for increased efficiency of processing compressed multimedia data: A method and system of processing compressed multimedia data using fine-grain instruction parallelism is provided. The method of processing multimedia data includes transferring an instruction from each of a plurality of sequencers to associated processing elements within an array of processing elements. The instructions can be processed by the array... Agent: Haverstock & Owens LLP

20080059764 - Integral parallel machine: The present invention is an integral parallel machine for performing intensive computations. By combining data parallelism, time parallelism and speculative parallelism where data parallelism and time parallelism are segregated, efficient computations can be performed. Specifically, for sequential functions, the time parallel system in conjunction with an implementation for speculative parallelism... Agent: Haverstock & Owens LLP

20080059765 - Coprocessor interface unit for a processor, and applications thereof: A coprocessor interface unit for interfacing a coprocessor to an out-of-order execution pipeline, and applications thereof. In an embodiment, the coprocessor interface unit includes an in-order instruction queue, a coprocessor load data queue, and a coprocessor store data queue. Instructions are written into the in-order instruction queue by an instruction... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080059757 - Convolver architecture for vector processor: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20080059758 - Memory architecture for vector processor: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20080059759 - Vector processor architecture: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20080059760 - Instructions for vector processor: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20080059761 - Fault tolerant cell array architecture: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing... Agent: Ogilvy Renault LLP

20080059762 - Multi-sequence control for a data parallel system: The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a... Agent: Haverstock & Owens LLP

20080059766 - Method and apparatus for improved programmable processor: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080059767 - Method and apparatus for performing improved group floating-point operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080059768 - Method and apparatus for communicating a bit per half clock cycle over at least one pin of an spi bus: Various embodiments increase the speed of communication over an SPI bus by communicating a bit per half clock cycle over at least one pin of an SPI bus.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080059769 - Multiple-core processor supporting multiple instruction set architectures: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080059770 - Superscalar risc instruction scheduling: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080059771 - Out-of-order processor having an in-order coprocessor, and applications thereof: An in-order coprocessor is interfaced to an out-of-order execution pipeline. In an embodiment, the interfacing is achieved using a coprocessor interface unit that includes an in-order instruction queue, a coprocessor load data queue, and a coprocessor store data queue. Instructions are written into the in-order instruction queue by an instruction... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080059772 - Method and system for increasing decoder throughput: A method for increasing decoder throughput is provided that includes dividing a data block into a plurality of segments. For each of the segments, the segment is decoded by performing a plurality of processes for the segment. At least one process for a current segment is performed while at least... Agent: Docket Clerk

20080059773 - Systems and methods using an invocation model of process expression: Invocation language is described that is suitable for controlling a machine to perform a process having concurrent parts. Each concurrent part has an association relationship, a completeness relation, and an invocation expression.... Agent: Steptoe & Johnson LLP

20080059774 - Instruction set with thermal opcode for high-performance microprocessor, microprocessor, and method therefor: A method (and system) of managing heat in an electrical circuit, includes using a thermal instruction appended to an instruction to be processed to determine a heat load associated with the instruction.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080059775 - Instruction set with thermal opcode for high-performance microprocessor, microprocessor, and method therefor: A method (and system) of managing heat in an electrical circuit, includes using a thermal instruction appended to an instruction to be processed to determine a heat load associated with the instruction.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080059776 - Compression method for instruction sets: A compression method and apparatus compresses the instruction for a CPU which significantly reduces the density of storage device of storing the program. Multiple groups of instructions are compressed separately by a mapping unit indicating the starting location of a group of instructions which helps quickly recovering the corresponding instructions.... Agent: Chih-ta Star Sung

20080059777 - Semiconductor integrated circuit device and compiler device: An execution program holder holds an execution program that includes execution instructions and configuration instructions that are executed together by a processor. A reconfigurable processing device comprises a programmable device that can reconfigure a circuit, and executes process contents that are instructed through executing the execution instructions by the processor.... Agent: Mcdermott Will & Emery LLP

20080059778 - Determination of running status of logical processor: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is... Agent: International Business Machines Corporation

20080059779 - Overriding a static prediction: In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments... Agent: Trop Pruner & Hu, PC

20080059780 - Methods and apparatus for emulating the branch prediction behavior of an explicit subroutine call: An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related... Agent: Qualcomm Incorporated