SEARCH:      Monitor Keywords |  Custom RSS

Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) February patents and inventions 02/08

20080052490 - Computational resource array: A sea of computational resources includes a number of computational resources, each of which is a member of one or more nearest neighbor pairings. Each nearest neighbor pairing has an upstream neighbor and a downstream neighbor, and each nearest neighbor pairing transfers data between the upstream neighbor and the downstream... Agent: Sylke Law Offices, LLC

20080052493 - Portable electronic device and processor therefor: A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores,... Agent: Huffman Law Group, P.C.

20080052494 - Method and device for operand processing in a processing unit: A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a... Agent: Kenyon & Kenyon LLP

20080052489 - Multi-pipe vector block matching operations: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20080052491 - Manifold array processor: An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the... Agent: Peter H. Priest

20080052492 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such... Agent: Glenn Patent Group

20080052495 - System and method of execution of register pointer instructions ahead of instruction issues: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides... Agent: James J. Bitetto, Esq. Keusey, Tutunjian & Bitetto, P.C.

20080052496 - Method and apparatus for priority based data processing: When performing simulation of a system having a plenty of components such as a physical phenomenon and a social phenomenon, there has been a problem that an enormous calculation time is required if the number of components increases. In order to solve this problem, an important component selection device is... Agent: Birch Stewart Kolasch & Birch

20080052497 - Parallel operation device allowing efficient parallel operational processing: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction Multiple Data (MIME) instruction and an MIMD register storing data designating the MIME instruction are provided, and an inter-ALU communication circuit is provided. The amount and... Agent: Buchanan, Ingersoll & Rooney PC

20080052498 - Runtime code modification in a multi-threaded environment: A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification... Agent: Ibm Corporation

20080052499 - Systems and methods for providing security for computer systems: Hardware and/or software countermeasures are provided to reduce or eliminate vulnerabilities due to the observable and/or predictable states and state transitions of microprocessor components such as instruction cache, data cache, branch prediction unit(s), branch target buffer(s) and other components. For example, for branch prediction units, various hardware and/or software countermeasures... Agent: Townsend And Townsend And Crew, LLP

20080052500 - Processor with branch predictor: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.... Agent: Brake Hughes Bellermann LLP

20080052501 - Filtered branch-prediction predicate generation: A method, of manipulating a raw branch history (RBH), can include: providing a RBH relevant to a conditional branching instruction in a program; and filtering the RBH to obtain a filtered branch-prediction predicate. A related method, of making a branch prediction, can include: manipulating, as in the above-mentioned method, a... Agent: Harness, Dickey & Pierce, P.L.C

20080046682 - Data processing unit and method for parallel vector data processing: P

20080046683 - System and method of processing data using scalar/vector instructions: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and... Agent: Qualcomm Incorporated

20080046684 - Multithreaded multicore uniprocessor and a heterogeneous multiprocessor incorporating the same: A uniprocessor that can run multiple threads (programs) simultaneously is achieved by use of a plurality of low-frequency minicore processors, each minicore for receiving a respective thread from a high-frequency cache and processing the thread. A superscalar processor may be used in conjunction with the uniprocessor to process threads requiring... Agent: Cantor Colburn LLP-ibm Yorktown

20080046685 - Methods and apparatus for independent processor node operations in a simd array processor: A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem)... Agent: Gerald G. Pechanek

20080046689 - Method and apparatus for cooperative multithreading: A cooperative multithreading architecture includes an instruction cache, capable of providing a micro-VLIW instruction; a first cluster, connects to the instruction cache to fetch the micro-VLIW instruction; and a second cluster, connects to the instruction cache to fetch the micro-VLIW instruction and capable of execution acceleration. The second cluster includes... Agent: Rosenberg, Klein & Lee

20080046681 - Two dimensional addressing of a matrix-vector register array: A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns.... Agent: Schmeiser, Olsen & Watts

20080046686 - Method and apparatus for an inductive doubling architecture: One embodiment of the present invention is a processor that processes inductive doubling SIMD instructions, which processor comprises: an Instruction Fetch Unit that loads a SIMD instruction and applies it as input to a SIMD Instruction Decode Unit; wherein the SIMD Instruction Decode Unit decodes the applied SIMD instruction and... Agent: Michael B. Einschlag, Esq.

20080046687 - Processor executing simd instructions: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero... Agent: Wenderoth, Lind & Ponack L.L.P.

20080046688 - Processor executing simd instructions: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero... Agent: Wenderoth, Lind & Ponack L.L.P.

20080046690 - Processor executing simd instructions: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero... Agent: Wenderoth, Lind & Ponack L.L.P.

20080046691 - Power reduction in microprocessor systems: A method is provided for reducing the power consumption of a pipelined microprocessor system arranged to run a program stored in a memory. The method comprises duplicating at least one branch instruction so as to reduce the number of transitions on the bus between the microprocessor and the memory when... Agent: At&t Corp.

20080046692 - Method and apparatus for executing processor instructions based on a dynamically alterable delay: Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In some embodiments, the dynamic delay is determined by an application to be executed by the processing system. In other embodiments, the dynamic delay... Agent: Qualcomm Incorporated

20080046694 - Multiprocessor system: A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the... Agent: Staas & Halsey LLP

20080046695 - System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function: In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of... Agent: Staas & Halsey LLP

20080046696 - Non-intrusive method for replaying internal events in an application process, and system implementing this method:

20080046693 - Secure digital processing unit and method for protecting programs: A digital processing unit for executing program instructions stored in at least two memories and including at least one first register of temporary storage of the operator of a current instruction to be executed and at least a second register of temporary storage of at least one argument or operand... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080046697 - Data processor: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has... Agent: Miles & Stockbridge PC

20080046698 - Run length encoding in vliw architecture: A computer implemented method of video date encoding generates a mask having one bit corresponding each spatial frequency coefficient of a block during quantization. The bit state of the mask depends upon whether the corresponding quantized spatial frequency coefficient is zero or non-zero. The runs of zero quantized spatial frequency... Agent: Texas Instruments Incorporated

20080046700 - Method and apparatus for efficient performance monitoring of a large number of simultaneous events: A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits... Agent: Scully Scott Murphy & Presser, PC

20080046699 - Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking: Methods and apparatus are provided for non-deterministic incremental program replay using checkpoints and syndrome tracking. Replay of a program proceeds by, for a given execution of the program, recording one or more checkpoints of the program, the one or more checkpoints containing program state information; and a recorded list of... Agent: Ryan, Mason & Lewis, LLP

20080046701 - Data processing apparatus and method for controlling access to registers: A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data values, the processing unit having a plurality of modes of operation. A plurality of registers are provided for storing data values for... Agent: Nixon & Vanderhye, PC

20080046702 - Methods and apparatus for reducing lookups in a branch target address cache: A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the... Agent: Qualcomm Incorporated

20080046703 - Context look ahead storage structures: A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the... Agent: James J. Bitetto, Esq. Keusey, Tutunjian & Bitetto, P.C.

20080046704 - Processor executing simd instructions: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero... Agent: Wenderoth, Lind & Ponack L.L.P.

20080040574 - Super-reconfigurable fabric architecture (surfa): a multi-fpga parallel processing architecture for cots hybrid computing framework: A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mapped from the virtual bus interface. A reconfigurable communication... Agent: Ingrassia Fisher & Lorenz, P.C. (boeing)

20080040575 - Parallel data processing apparatus: A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements in which the processing elements are arranged in a plurality of SIMD processing blocks, comprises determining which instruction stream has priority at a particular moment in time, and transferring that determined instruction stream... Agent: Glenn Patent Group

20080040576 - Associate cached branch information with the last granularity of branch instruction in variable length instruction set: In a variable-length instruction set wherein the length of each instruction is a multiple of a minimum instruction length granularity, an indication of the last granularity (i.e., the end) of a taken branch instruction is a stored in a branch target address cache (BTAC). If a branch instruction that later... Agent: Qualcomm Incorporated

20080040577 - Method and apparatus for improved computer load and store operations: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence... Agent: Huffman Law Group, P.C.

20080040579 - Methods and apparatus for handling switching among threads within a multithread processor: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution... Agent: Schwabe, Williamson & Wyatt, P.C.

20080040578 - Multi-thread processor with multiple program counters: A system, apparatus and method for an interleaving multi-thread processing device are described herein. The multi-thread processing device includes an execution block to execute instructions and a fetch block to fetch and issue instructions, interleavingly, of a first instruction execution thread and at least one other instruction execution thread. The... Agent: Schwabe, Williamson & Wyatt, P.C.

20080040580 - Microcontroller based flash memory digital controller system: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from... Agent: Sawyer Law Group LLP

20080040581 - Pipelined asynchronous instruction processor circuit: A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective... Agent: Philips Intellectual Property & Standards

20080040582 - Data processing unit and data processing apparatus using data processing unit: A storage unit retains processing target data, a data processing circuit processes the data retained in the storage unit, a connection unit is connected to a processing device that executes a computer program, and a control unit invalidates, when a predetermined condition is detected, the data processing by the data... Agent: Arent Fox LLP

20080040583 - Digital data processing apparatus having asymmetric hardware multithreading support for different threads: Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. Preferably, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for use by a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080040584 - Method and apparatus for performing group floating-point operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080040585 - Methods and apparatus for attaching application specific functions within an array processor: A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters... Agent: Gerald G. Pechanek

20080040586 - Predicated execution using operand predicates: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is... Agent: Stmicroelectronics, Inc.

20080040587 - Debug circuit comparing processor instruction set operating mode: A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication... Agent: Qualcomm Incorporated

20080040588 - Data processing device and data processing method: An undo technique with improved ease-of-use is provided. A document processing apparatus executes editing, printing, and storage for a document file. An undo manager records the operation history of the document processing apparatus in an undo stack. Upon reception of an instruction from a user to undo an operation, the... Agent: Sughrue Mion, PLLC

20080040589 - Processor device: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS... Agent: Staas & Halsey LLP

20080040592 - Control of a branch target cache within a data processing system: A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions... Agent: Nixon & Vanderhye, PC

20080040591 - Method for determining branch target buffer (btb) allocation for branch instructions: A method of profiling each of a plurality of branch instructions to determine when allocation of an entry in a branch target buffer should occur if the branch is taken. Various factors are used in the determination. In one form, each of the plurality of branch instructions is analyzed to... Agent: Freescale Semiconductor, Inc. Law Department

20080040590 - Selective branch target buffer (btb) allocaiton: Information is processed in a data processing system having a branch target buffer (BTB). In one form, an instruction is received and decoded. A determination is made whether the instruction is a taken branch instruction based on a condition code value set by one of a logical operation, an arithmetic... Agent: Freescale Semiconductor, Inc. Law Department

20080040593 - Embedded software camouflage against code reverse engineering: Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will continue after execution of the first instruction. A determination is made as to whether the first program address is protected. If... Agent: Fish & Richardson P.C.

20080034184 - Fault tolerant cell array architecture: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing... Agent: Ogilvy Renault LLP

20080034185 - Parallel data processing apparatus: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.... Agent: Glenn Patent Group

20080034186 - Parallel data processing apparatus: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.... Agent: Glenn Patent Group

20080034188 - Information processing apparatus and method for accelerating information processing: An apparatus comprises an instruction execution control unit which fetches an instruction executed according to a microinstruction, the instruction is classified into a plurality of types, from a memory, wherein the types include a first type indicative of generating a condition code and a second type indicative of not generating... Agent: Young & Thompson

20080034187 - Method and apparatus for prefetching non-sequential instruction addresses: A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is... Agent: Qualcomm Incorporated

20080034189 - Method and system to perform shifting and rounding operations within a microprocessor: A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a... Agent: Qualcomm Incorporated

20080034190 - Method and apparatus for suspending execution of a thread until a specified memory access occurs: Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes... Agent: Intel/blakely

20080034191 - Image communication terminal and method of processing image communication data in image communication terminal: Disclosed is an image communication terminal including a main processor that controls operation in accordance with image communications, decodes video data, and encodes images photographed through a camera, and a modem processor that processes data in accordance with radio communications, divides image communication data into video and audio data, and... Agent: The Farrell Law Firm, P.C.

20080034192 - Register with a context switch device and method of context switching: A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from... Agent: Qualcomm Incorporated

20080034194 - Method and apparatus for using a 32-bit operating system kernel to support 64-bit applications: One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by executing OS kernel code. Specifically, the exception... Agent: Apple Computer, Inc. C/o Park, Vaughan & Fleming LLP

20080034193 - System and method for providing a mediated external exception extension for a microprocessor: A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so,... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.