FREE patent keyword monitoring and additional FREE benefits. /images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
Fresh Patents freshpatentsnav7_icons (5K)
browse patent apps by agents browse patent apps by inventors browse patent apps by industry browse patents by location monitor patent applications
    



USPTO Class 712  |  Browse by Industry: Previous - Next | All     monitor keywords
01/2008 | Recent  |  08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 07: D | N | O | S | A | J | J | M | A | M | F | J |  | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov |  | 2010 | 2009 |

    SEARCH:      Monitor Keywords | rss Custom RSS

Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) January USPTO class listing 01/08

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/31/2008 > patent applications in patent subcategories. USPTO class listing

20080028187 - Configurable processor module accelerator using a programmable logic device: A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department

20080028183 - Processor architecture for multipass processing of instructions downstream of a stalled instruction: A processor triggers a first advanced execution processing pass to an instruction sequence in response to a stalled instruction and initiates execution of a further instruction in the instruction sequence that stalls during the performance of the first advance execution processing pass. A second advance execution pass is performed through... Agent: Krieg Devault LLP

20080028184 - Parallel data processing apparatus: A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel... Agent: Glenn Patent Group

20080028185 - Network-extensible reconfigurable media appliance: Extensible reconfigurable media appliance for security and entertainment captures images digitally for storage. Digital effects and filters are applied to incoming video stream on-the-fly or to video data stored in memory. Digital effects and filters are dynamically stored, modified, updated or deleted, providing extensible reconfigurable effects studio. Digital media appliance... Agent: Fernandez & Associates LLP

20080028186 - Fpga co-processor for accelerated computation: A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department

20080028188 - Time de-interleaver implementation using sdram in a tds-ofdm receiver: A receiver having an apparatus having a processor for processing interleaved data; and an independent memory coupled to the processor for processing the interleaved data is provided.... Agent: Frank F. Tian

20080028189 - Microprocessor and method of instruction alignment: Therefore, a microprocessor for processing instructions is provided. Said microprocessor comprises a cache for caching instructions and/or data to be processed, which are arranged in cache words, and an alignment unit for aligning instructions to predetermined positions with regard to cache word boundaries of said cache by introducing padding bytes... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080028190 - System controller for flash memory: A system controller exchanges data with a memory controller. The system controller includes an interpreting unit, a first instruction data supplying unit, a second instruction data supplying unit, and a controlling unit. The second instruction data supplying unit transfers the first operation instruction data provided from a host system to... Agent: Oliff & Berridge, PLC

20080028191 - Instruction set and information processing apparatus: An instruction set and an information processing apparatus are provided that improve parallelity of a program by using comparatively simple means. A method is provided in which in addition to a mnemonic assigned to an operation code of an instruction under present execution of a program, at least one or... Agent: Stevens, Davis, Miller & Mosher, LLP

20080028192 - Data processing apparatus, and data processing method: The present invention provides a data processing apparatus includes a plurality of register units and an operation unit. Each of the plurality of register units includes a register divided into a plurality of blocks, each of the plurality of blocks capable of holding a block data being at least 1... Agent: Mcginn Intellectual Property Law Group, PLLC

20080028193 - Transitive suppression of instruction replay: In one embodiment, a processor comprises one or more execution resources configured to execute instruction operations and a scheduler coupled to the execution resources. The scheduler is configured to maintain an ancestor tracking vector (ATV) corresponding to each given instruction operation in the scheduler, wherein the ATV identifies instruction operations... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080028194 - Efficient interrupt return address save mechanism: A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request... Agent: Qualcomm Incorporated

20080028195 - Method and apparatus for saving and restoring processor register values and allocating and deallocating stack memory: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080028196 - Method and apparatus for fast synchronization and out-of-order execution of instructions in a meta-program based computing system: A method and structure for an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other. The synchronization is achieved by monitoring addresses of instructions in at least one of the threads.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080028197 - Data transfer control device including endian conversion circuit: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in... Agent: Mcdermott Will & Emery LLP

  
01/24/2008 > patent applications in patent subcategories. USPTO class listing

20080022069 - Register file regions for a processing system: According to some embodiments, a dynamic region in a register file may be defined for an operand. The defined region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the... Agent: Buckley, Maschoff & Talwalkar LLC

20080022070 - Programmable image readout sequencer: A programmable sequencer for a solid-state image sensor provides hard/soft configurable control of imaging operations in an imaging core.... Agent: Blakely Sokoloff Taylor & Zafman

20080022071 - Computerized system for simultaneous operation of multiple environments securing and separating digitally stored data: A computerized system for simultaneous operation of multiple environments and method for storing distinct data types separately is disclosed. The computerized system includes a plurality of main host, sub-host, data storage and network devices wherein data of a first type is stored on main host, data storage and network devices... Agent: Mark Andrew Reid

20080022072 - System, method and medium processing data according to merged multi-threading and out-of-order scheme: A system, method and medium performing data operations according to a merged multi-threading and out-of-order scheme. According to the method, at least one instruction is decoded, a thread of an instruction is read based on the decoding result, and a predetermined operation is performed on each of a plurality of... Agent: Staas & Halsey LLP

20080022073 - Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length... Agent: Mark A Lauer

20080022074 - Instruction length decoder: Methods and apparatus relating to speculatively decoding instruction lengths in order to increase instruction throughput are described. In an embodiment, instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles. Other embodiments are... Agent: Caven & Aghevli C/o Intellevate

20080022075 - Systems and methods for processing buffer data retirement conditions: Systems and methods for determining whether to retire a data entry from a buffer using multiple retirement logic units. In one embodiment, each retirement unit concurrently evaluates retirement conditions for one of the buffer entries in an associated subset (e.g., even or odd) of the buffer. Selection logic coupled to... Agent: Law Offices Of Mark L. Berrier

20080022076 - Operating system thread scheduling for optimal heat dissipation: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers.... Agent: Scully Scott Murphy & Presser, PC

20080022077 - Processor having a compare extension of an instruction set architecture: A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080022078 - System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080022080 - Data access handling in a data processing system: A data processing system is provided comprising fetching logic for fetching program instructions for execution, a first data-accessing unit for handling decoding and execution of data access instructions and a second data-accessing unit for handling decoding and execution of program-counter-relative data access instructions. Handling of the program-counter-relative data access instructions... Agent: Nixon & Vanderhye, PC

20080022079 - Executing an allgather operation with an alltoallv operation in a parallel computer: Executing an allgather operation on a parallel computer, including executing an alltoallv operation with a list of send displacements, where each send displacement is a send buffer segment pointer, each send displacement points to the same segment of a send buffer, the parallel computer includes a plurality of compute nodes,... Agent: Ibm (roc-blf)

20080022081 - Local controller for reconfigurable processing elements: A reconfigurable computer is disclosed. The computer includes a controller and at least one reconfigurable processing element communicatively coupled to the controller. The controller is operable to read at least a first portion of a respective configuration of each of the plurality of reconfigurable processing elements and refresh at least... Agent: Honeywell International Inc.

20080022082 - Start transactional execution (ste) instruction to support transactional program execution: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

  
01/17/2008 > patent applications in patent subcategories. USPTO class listing

20080016317 - Method and arrangement for cache memory management, related processor architecture: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080016319 - Processor architecture, for instance for multimedia applications: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080016321 - Interleaved hardware multithreading processor architecture: An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As... Agent: Brinks Hofer Gilson & Lione

20080016318 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array.... Agent: Glenn Patent Group

20080016320 - Vector predicates for sub-word parallel operations: This invention uses vector predicate registers to control conditional execution of instructions for vector elements within a data word. A particular vector predicate registers is addressed via a register index. The state of bits of the vector predicate register controls whether a corresponding sub-word operation is executed or inhibited.... Agent: Texas Instruments Incorporated

20080016322 - Fast aggregation of compressed data using full table scans: Methods and apparatus, including computer systems and program products, relating to an information management system and aggregating data by performing table scans. In general, in one aspect, the technique includes receiving a query for a response to a search on a database, loading data from the database into memory, filtering... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.

20080016323 - Early access to microcode rom: An apparatus and method are provide for precluding stalls in a microprocessor pipeline due to microcode ROM access delay. The apparatus includes a micro instruction queue and early access logic. The micro instruction queue provides a plurality of queue entries to register logic. Each of tile plurality of queue entries... Agent: Huffman Law Group, P.C.

20080016326 - Latest producer tracking in an out-of-order processor, and applications thereof: A processor and system for latest producer tracking. In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080016324 - Method and apparatus for register renaming using multiple physical register files and avoiding associative search: A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of... Agent: Cantor Colburn LLP-ibm Yorktown

20080016325 - Using windowed register file to checkpoint register state: In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management unit is configured to operate the plurality of storage locations as a plurality of windows, wherein register addresses encoded into the... Agent: Mhkkg/sun

20080016327 - Register file bypass with optional results storage and separate predication register file in a vliw processor: This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next... Agent: Texas Instruments Incorporated

20080016328 - Information processing equipment and method of changing processor function: An information processing equipment comprises: a processor configured to refer to a function information indicating an assigned function and to execute a firmware code corresponding to the function information; and a memory in which the firmware code and the function information are stored. The information processing equipment further comprises a... Agent: Young & Thompson

20080016329 - Structure of sequencers that perform initial and periodic calibrations in a memory system: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers.... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080016330 - efficient multiple-table reference prediction mechanism: A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are... Agent: Dillon & Yudell LLP

  
01/10/2008 > patent applications in patent subcategories. USPTO class listing

20080010435 - Memory systems and memory modules: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature.... Agent: Patterson & Sheridan, LLP Metaram

20080010434 - Transmission apparatus, reception apparatus, and transmission/reception method for same: A receiving station repeatedly performs decoding processing of data in a decoding processing portion, performs error detection of the decoding results, and transmits to a transmitting station an error detection result (ACK/NACK) for decoding results for a preset number of executions, and moreover issues a request to the transmitting station... Agent: Bingham Mccutchen LLP

20080010436 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.... Agent: Glenn Patent Group

20080010437 - Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (fpgas): An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system,... Agent: Michelle M. Carniaux, Esq. Kenyon & Kenyon

20080010438 - Memory with an output register for test data and process for testing a memory and memory module: The invention relates to a memory with a memory array with memory cells, with an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, with an output register which is connected to the input/output circuit, with the output register being used to... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20080010439 - Variable length decoder system and method: Simultaneously decoding one or more variable length code symbols including storing in a bit FIFO at least a portion of a variable length coded bit stream; storing a succession of extracted bit fields of predetermined bit length from the variable length coded bit stream in the bit FIFO; defining at... Agent: Iandiorio & Teska

20080010441 - Means for supporting and tracking a large number of in-flight loads in an out-of-order processor: A method for supporting and tracking a plurality of loads in an out-of-order processor being run by a program includes executing instructions on the processor, the instructions including an address from which data is to be loaded and memory locations from which load data is received, determining inputs of the... Agent: Cantor Colburn LLP-ibm Yorktown

20080010440 - Means for supporting and tracking a large number of in-flight stores in an out-of-order processor: A method for supporting and tracking a plurality of stores in an out-of-order processor run by a predetermined program includes executing a plurality of instructions on the processor, each instruction including an address from which data is to be loaded and a plurality of memory locations from which load data... Agent: Cantor Colburn LLP-ibm Yorktown

20080010442 - Mechanism to save and restore cache and translation trace for fast context switch: A method and system for efficient context switching are provided. An execution entity that is to be context switched out is allowed to continue executing for a predetermined period of time before being context switched out. During the predetermined period of time in which the execution entity continues to execute,... Agent: Scully Scott Murphy & Presser, PC

20080010443 - System and method for executing conditional branch instructions in a data processor: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations.... Agent: Stmicroelectronics, Inc.

20080010444 - Elimination of stream consumer loop overshoot effects: A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore... Agent: Hogan & Hartson LLP

Previous industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support


######

RSS FEED for 20140710: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.



Results in 0.3453 seconds

PATENT INFO