Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 12/07

20070300040 - Method for resource sharing in a multiple pipeline environment: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to... Agent: International Business Machines Corporation

20070300045 - Device and methods for coping with inefficiency from general purpose processors in implementing algorithms: A circuit to detect position signals in a mobile station includes a general-purpose processor to generate instructions for execution of at least one signal detection algorithm and to carry out at least one other function not associated with the signal detection algorithm, special-purpose hardware blocks responsive to the instructions of... Agent: Qualcomm Incorporated

20070300042 - Method and apparatus for interfacing a processor and coprocessor: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and... Agent: Freescale Semiconductor, Inc. Law Department

20070300043 - Method and apparatus for interfacing a processor and coprocessor: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and... Agent: Freescale Semiconductor, Inc. Law Department

20070300044 - Method and apparatus for interfacing a processor and coprocessor: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and... Agent: Freescale Semiconductor, Inc. Law Department

20070300041 - Method for processing streaming data in a multiprocessor system: The present invention relates to a method for processing streaming data in a multiprocessor system. In this method, in a pipelining architecture of the multiprocessor system a specified number of processors having a specified number of programs processes, in a clocked manner, a number of data packets which are inputted... Agent: Siemens Corporation Intellectual Property Department

20070300047 - Reconfigurable processor integrated circuit: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins,... Agent: Howison & Arnott, L.l.p

20070300046 - System and method for programming integrated circuit package via jtag interface: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A flash memory stores instructions within the integrated circuit package. A plurality of registers stores data and the program instructions during execution of the program instructions. A JTAG interface provides... Agent: Howison & Arnott, L.l.p

20070300048 - System and method for targeting commands to concurrent computing units executing a concurrent computing process: A graphical user interface for a concurrent computing environment that conveys the concurrent nature of a computing environment and allows a user to monitor the status of a concurrent process being executed on multiple concurrent computing units is discussed. The graphical user interface allows the user to target specific concurrent... Agent: Lahive & Cockfield, LLP

20070300049 - Technique to perform three-source operations: A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.... Agent: Trop Pruner & Hu, PC

20070294507 - Asymmetric clustered processor architecture based on value content: A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster... Agent: Shimokaji & Associates, P.C.

20070294508 - Parallel pseudorandom number generation: A method of generating pseudo-random numbers on a parallel processing system comprises generating a plurality of sub-streams of pseudo-random numbers, wherein the sub-streams are generated in parallel by one or more co-processors, and providing the plurality of sub-streams to respective processing elements, wherein the respective processing elements employ the plurality... Agent: Morgan, Lewis & Bockius, LLP.

20070294509 - Network processor: The invention relates to a network processor provided with a plurality of programmable processor elements. One part of the plurality of processor elements is embodied as interface processor elements which are used to provide an output communication interface and/or an input communication interface according to a communication processor for the... Agent: Dickstein Shapiro LLP

20070294510 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to determine which of a plurality of instruction streams has priority at a particular moment in time, and to transfer that instruction stream to the SIMD array.... Agent: Glenn Patent Group

20070294511 - Programmable processor architecture: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than... Agent: Law Offices Of Imam

20070294512 - Systems and methods for dynamically choosing a processing element for a compute kernel: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance... Agent: Morgan, Lewis & Bockius, LLP.

20070294513 - Facilitating fast scanning for control transfer instructions in an instruction fetch unit: One embodiment of the present invention provides a system that performs a fast-scanning operation to generate fetch bundles within an instruction fetch unit (IFU) of a processor. During operation, the system obtains a cache line containing instructions at the IFU. Next, the system performs a complete-scanning operation on the cache... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070294514 - Picture processing engine and picture processing system: To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070294515 - Register file bit and method for fast context switch: A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the primary... Agent: Martin & Associates, LLC

20070294516 - Switch prefetch in a multicore computer chip: Systems and methods for switch prefetch in multicore computer chips can allow a programmer to tailor operations of a computer program to available data. Control-flow decisions can be made by the program based on the availability of data in a cache. For example, a new instruction in a processor instruction... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070294517 - Method and device for saving and restoring a set of registers of a microprocessor in an interruptible manner: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the... Agent: Seed Intellectual Property Law Group PLLC

20070294518 - System and method for predicting target address of branch instruction utilizing branch target buffer having entry indexed according to program counter value of previous instruction: A system for determining the target address of a branch instruction is disclosed. The system includes: a branch target buffer (BTB), containing at least an entry storing the target address of the branch instruction, the entry being indexed according to a program counter (PC) value of an instruction prior to... Agent: North America Intellectual Property Corporation

20070294519 - Localized control caching resulting in power efficient control logic: An integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the... Agent: Downs Rachlin Martin PLLC

20070288734 - Double-width instruction queue for instruction execution: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, issuing instructions for a first path of the branch instruction to a first queue of a dual instruction queue, and issuing instructions for a second path of the branch instruction... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070288733 - Early conditional branch resolution: A method and apparatus for executing branch instructions is provided. In one embodiment, In one embodiment, the method includes receiving the branch instruction to be executed in a program order and, before execution of the branch instruction in the program order, issuing the branch instruction to an execution unit to... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070288732 - Hybrid branch prediction scheme: A method and apparatus for executing a branch instruction is provided. In one embodiment, the method includes determining if a predictability value for the branch instruction is below a threshold value. Upon determining that the predictability value is above or equal to the threshold value, branch prediction information for the... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070288735 - Branch prediction within a multithreaded processor: A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behaviour and the prediction... Agent: Nixon & Vanderhye, PC

20070288736 - Local and global branch prediction information storage: Embodiments of the invention provide a method and apparatus of storing branch prediction information. In one embodiment, the method includes receiving a branch instruction and storing local branch prediction information for the branch instruction including a local predictability value for the local branch prediction information. The method further includes storing... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070283128 - Asymmetric multiprocessor: An asymmetric multiprocessor capable of increasing the degree of freedom of distributed processing, minimizing the processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing the operating frequency or lowering the power supply voltage. Asymmetric multiprocessor (100) includes a hardware resource mediation section (110)... Agent: Greenblum & Bernstein, P.L.C

20070283129 - Vector length tracking mechanism: According to one embodiment, a method is disclosed. The method includes receiving a value at a vector length (VL) tracker and establishing a VL for subsequent micro-operations (μops) that are to be executed corresponding to the value.... Agent: Blakely Sokoloff Taylor & Zafman

20070283130 - Compact storage of program code on mobile terminals: A memory space saving storage of program code is provided on an electronic equipment for wireless communication, by providing a respective electronic equipment (1) comprising first storage means (2) for a non-volatile storage of data, program code data (100, 101, 100′, 103, 101′) stored in the first storage means (2),... Agent: Warren A. Sklar (soer) Renner, Otto, Boisselle & Sklar, LLP

20070283131 - Processing of high priority data elements in systems comprising a host processor and a co-processor: To provide for the processing of priority data elements between a host processor and a co-processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20070283132 - End-of-block markers spanning multiple blocks for use in video coding: The present invention involves the use of the FRExt approach for FGS. According to the present invention, an 8×8 data block is de-interleaved and processed as individual 4×4 data blocks, with an additional end-of-8×8-block (EO8B) marker indicating that no more coefficients remain in any of the de-interleaved 4×4 data blocks.... Agent: Foley & Lardner LLP

20070283133 - Reducing bandwidth required for trace data: A data processing apparatus is disclosed comprising: trace logic for monitoring behaviour of a portion of said data processing apparatus; and prediction logic operable to provide at least one prediction as to at least one step of said behaviour of said portion of said data processing apparatus; wherein said trace... Agent: Nixon & Vanderhye, PC

20070283134 - Sliding-window, block-based branch target address cache: A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond... Agent: Qualcomm Incorporated

20070283135 - Multi-processor system and program execution method in the system: In a multi-processor system (100), when a first processor interrupt generation unit (24) has executed a call command or a jump command in a main routine being executed, it generates an interrupt to a second processor. Upon reception of the interrupt from the interrupt generation unit (24), the second processor... Agent: Katten Muchin Rosenman LLP