Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 11/07

20070277019 - Communication interface device and communication method: A first storing unit stores therein a chain indivisibility instruction. A detecting unit detects a change of first data that is distributed in a node computer. A first designating unit designates, when the detecting unit detects the change in the first data, an indivisibility instruction corresponding to the first data... Agent: Staas & Halsey LLP

20070277020 - Optimization of subsystem interconnections in an electronic device: A subprocessor is used to interface between subsystems and to reduce the amount of dedicated hardware used to implement the subsystems in a hand-held computer. The subprocessor includes basic processing system resources such as random-access memory (RAM), read-only memory (ROM), a processor, input/output (I/O) facilities, etc. Selected functions in subsystems... Agent: Trellis Intellectual Property Law Group, PC

20070277021 - Instruction folding for a stack-based machine: An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction sequences and supplies... Agent: Gunnison Mckay & Hodgson, LLP

20070277022 - Method, system and program product for establishing decimal floating point operands for facilitating testing of decimal floating point instructions: A method, system and program product are provided for establishing one or more decimal floating point (DFP) operand for facilitating testing of a decimal floating point instruction. The method includes obtaining an encoded DFP operand previously generated for testing the decimal floating point instruction, and logically modifying at least one... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070277023 - Method for switching over between at least two operating modes of a processor unit, as well corresponding processor unit: A method for switching over between at least two operating modes of a processor unit, having at least two execution units is provided, in which method a change from a first operating mode to a second operating mode is triggered by the processor unit accessing a predefined memory address.... Agent: Kenyon & Kenyon LLP

20070277024 - Methods and systems for secure address handling in a processor: An embodiment generally pertains to a method of secure address handling in a processor. The method includes detecting an instruction that implicitly designates a target address and retrieving an encoded location associated with the target address. The method also includes decoding the encoded location to determine the target address. Another... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20070277025 - Method and system for preventing livelock due to competing updates of prediction information: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is... Agent: Duke W. Yee

20070277026 - Processor, method, and data processing system employing a variable store gather window: A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain... Agent: Dillon & Yudell LLP

20070271440 - Computer processor architecture selectively using finite-state-machine for control code execution: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in... Agent: Wayne L. Tang Nixon Peabody, LLP.

20070271441 - Availability of space in a risc microprocessor architecture: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A... Agent: Henneman & Associates, PLC

20070271442 - Detecting the boundaries of memory in a risc microprocessor architecture: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A... Agent: Henneman & Associates, PLC

20070271443 - Data processing device: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from... Agent: Buchanan, Ingersoll & Rooney PC

20070271444 - Using register readiness to facilitate value prediction: One embodiment of the present invention provides a system for using register readiness to facilitate value prediction. The system starts by loading a previously computed result for a function to a destination register for the function from a lookup table. The system then checks the destination register for the function... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070271445 - Selectively monitoring stores to support transactional program execution: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070271446 - Application execution device and application execution device application execution method: The conventional application protection technique complicates an application to make it difficult to analyze the application. However, with such a complication method, the complicate program can be analyzed sooner or later by taking a lot of time no matter how the degree of the complication is high. Also, it is... Agent: Wenderoth, Lind & Ponack L.L.P.

20070271447 - Efficient transfer of branch information: A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to generate a branch packet comprising branch bits. At least some of the branch bits are associated with branch instructions executed by the processor. The trace logic... Agent: Texas Instruments Incorporated

20070271448 - Merging branch information with sync points: A method comprises determining whether a sync point is to be generated concurrent with a branch instruction and generating said sync point to include a program counter value and to indicate that the sync point occurred concurrent with the branch instruction.... Agent: Texas Instruments Incorporated

20070271449 - System and method for dynamically adjusting pipelined data paths for improved power management: A system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, includes a state machine is configured to determine an optimum length of a pipeline architecture based on a processing function to be performed, and a pipeline sequence controller,... Agent: Cantor Colburn LLP-ibm Burlington

20070271450 - Method and system for enhanced thread synchronization and coordination: Synchronization and communication between concurrent software threads is enhanced. An attempt may be made to acquire a lock associated with a resource. If the lock is not available and/or the attempt fails, a hardware monitor may be configured to detect release of the lock. An asynchronous procedure call responsive to... Agent: Intel Corporation C/o Intellevate, LLC

20070266223 - Network-on-chip dataflow architecture: With the development of microelectronic industry, we can integrate more and more transistors in a single chip. According to Moore's law, the number of transistors can double in 18 months. Therefore, our target is how to convert the number of transistors to the performance of microprocessors as well as DSPs.... Agent: Tran Le Nguyen

20070266224 - Method and computer program product for executing a program on a processor having a multithreading architecture: The method for executing a program on a processor having a multithreading architecture includes identifying at least two processes of the program, the processes being executable independently of one another in a parallel manner and essentially using the same joint resources. The at least two identified processes are associated with... Agent: Edell, Shapiro & Finnan, LLC

20070266225 - Microcontroller unit: A microcontroller unit (MCU) includes a CPU, a system integration module (SIM), and a memory. The CPU decodes instructions to determine the function, an addressing type and an operand address, and converts the operand address to a first address. The SIM converts the first address to a memory address. The... Agent: Freescale Semiconductor, Inc. Law Department

20070266226 - Method and system to combine corresponding half word units from multiple register units within a microprocessor: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within... Agent: Qualcomm Incorporated

20070266227 - Extended register space apparatus and methods for processors: Methods and apparatus for accessing an extended register space associated with a processor are disclosed. In an example method, an instruction indicating a tag value is received. It is then determined whether information is stored in a first group of registers or a second group of registers based on a... Agent: Hanley, Flight & Zimmerman, LLC

20070266228 - Block-based branch target address cache: A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken... Agent: Qualcomm Incorporated

20070266229 - Encoding hardware end loop information onto an instruction: Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is... Agent: Qualcomm Incorporated

20070266230 - Information processing method and instruction generating method: According to a generated instruction, the present invention provides an information processing method for performing processing by using a CPU that comprises at least one register. The method comprises the steps of: judging whether or not each of the registers is valid in the instruction; identifying a register whose value... Agent: Mcdermott Will & Emery LLP

20070260847 - Reconfigurable integrated circuit: A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks... Agent: Mcginn Intellectual Property Law Group, PLLC

20070260848 - Power mangement integrated circuit: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.... Agent: Intel/blakely

20070260849 - Method and apparatus for executing instrumentation code using a target processor: A computer implemented method, apparatus, and computer program product for executing instructions. A first processor identifies a target processor in response to the first processor executing a plurality of instructions in an instrumentation mode. The processor designates the target processor to execute instrumentation instructions associated with the plurality of instructions... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070260850 - Data transferring method, and communication system and program applied with the method: Disclosed is a communication system that transmits data through a transmission path between a transmission side apparatus and a reception side apparatus, wherein the transmission side apparatus comprises a coding apparatus that creates redundantly-coded data from original data; a transmitting apparatus that sends the coded data coded by the coding... Agent: Staas & Halsey LLP

20070260851 - Sleep optimization based on system information block scheduling: Methods and apparatuses are presented for sleep optimization based on system information block SIB scheduling. A method for invoking sleep states within user equipment (UE) is presented. The method includes decoding a broadcast control channel with a cell, determining a System Information Block (SIB) schedule associated with the cell, determining... Agent: Qualcomm Incorporated

20070260852 - Fetch and dispatch disassociation apparatus for multi-streaming processors: A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and... Agent: Huffman Law Group, P.C.

20070260853 - Switching processor threads during long latencies: In one embodiment, the present invention includes an apparatus to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the instruction may require the long latency. In certain embodiments, at least one additional instruction may be executed... Agent: Trop Pruner & Hu, PC

20070260855 - Method and apparatus for the dynamic creation of instructions utilizing a wide datapath: A processing system and method includes a predecoder configured to identify instructions that are combinable. Instruction storage is configured to merge instructions that are combinable by replacing the combinable instructions with a wide data internal instruction for execution. An instruction execution unit is configured to execute the internal instruction on... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070260854 - Pre-decoding variable length instructions: A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering... Agent: Qualcomm Incorporated

20070260856 - Methods and apparatus to detect data dependencies in an instruction pipeline: Example methods and apparatus to detect data dependencies in an instruction pipeline are disclosed. A disclosed example method uses an address pointer associated with a first instruction and indicates a first data dependency status of the first instruction. The example method then indicates a second data dependency status of the... Agent: Texas Instruments Incorporated

20070260857 - Electronic circuit: There is provided an electronic circuit adapted to process a plurality of types of instruction, the electronic circuit comprising first and second pipeline stages and a latch positioned between the pipeline stages; wherein the electronic circuit is adapted to operate in a normal mode when processing a first type of... Agent: Philips Intellectual Property & Standards

20070260858 - Processor and processing method of the same: There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next from an instruction cache memory or from a main memory, to... Agent: Staas & Halsey LLP

20070260860 - Method and apparatus for executing instrumentation code using processor instructions: A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing the instructions using a normal set of processor resources in a processor. Subsequent instructions... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070260859 - Method and apparatus for executing instrumentation code within alternative processor resources: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and an alternate set of resources in which the alternate set... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070260861 - Method and system for controlling timing in a processor: A method and system for controlling timing in a processor. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and wherein each instruction has a second default execution time during a... Agent: Sawyer Law Group LLP

20070260862 - Providing storage in a memory hierarchy for prediction information: In one embodiment, the present invention includes an apparatus having a prediction unit to predict a direction to be taken at a branch and a memory coupled to the prediction unit to store prediction data to be accessed by the prediction unit. In this way, great amounts of prediction data... Agent: Trop Pruner & Hu, PC

20070260863 - Integrated circuit having a conditional yield instruction and method therefor: An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are... Agent: Freescale Semiconductor, Inc. Law Department

20070255929 - Multiprocessor system and multigrain parallelizing compiler: Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system... Agent: Stanley P. Fisher Reed Smith

20070255930 - Processing a data word in a plurality of processing cycles: The invention relates to a processing of a data word in a plurality of processing cycles. In order to improve the efficiency of the processing, the data word is divided for each cycle into a plurality of successive data blocks. The blocks are shifted by one block from one cycle... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070255931 - Processing unit for generating control signal, controller with the processing unit for controlling actuator, and program executed in the processing unit: A controller with a processing unit and a floating-point processor is disposed in a vehicle to control an actuator according to detected parameters sent from sensors. The processor generates a floating-point control parameter indicating a first quantity of control from the detected parameters at floating-point calculations, and the unit generates... Agent: Nixon & Vanderhye, PC

20070255932 - Data processor and data process method: A data processor includes a reader for reading a bit stream stored in a storage if there is free space of 8 bits or more in a buffer and outputting to a first array changer, the first array changer for changing an array sequence of the 8 bits in reversed... Agent: Young & Thompson

20070255933 - Parallel condition code generation for simd operations: A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in respective corresponding fields of the at least two registers to create a plurality of condition values. Second control circuitry performs one... Agent: Freescale Semiconductor, Inc. Law Department