Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 10/07

20070250681 - Independent programmable operation sequence processor for vector processing: The present invention provides methods, systems and apparatus to control instruction sequencing for a vector processor in a parallel processing environment. It enhances standard Vector Processing architectures by using two independent processing units working in conjunction to produce a highly efficient data processing ensemble. In an example embodiment, the two... Agent: Louis Paul Herzberg

20070250682 - Method and apparatus for operating a computer processor array: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output... Agent: Henneman & Associates, PLC

20070250683 - Alignment and ordering of vector elements for single instruction multiple data processing: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070250684 - Central processing unit having a micro-code engine: A digital camera having a central processing unit with an embedded micro-code engine comprises a system memory capable of storing an instruction, at least one CPU execution unit electrically coupled with the system memory, and at least one micro-code engine electrically coupled with the CPU execution unit. The at least... Agent: Rosenberg, Klein & Lee

20070250685 - Operation-processing device, method for constructing the same, and operation-processing system and method: As shown in FIG. 1, an operation-processing device of the present invention comprises a register array (11) having plural registers for holding an arbitrary value based on a write address Aw and a write control signal Sw and outputting this value based on a read address Ar, an ALU (12)... Agent: Frommer Lawrence & Haug

20070250686 - Instruction processing circuit: An instruction processing circuit comprises an instruction decoder (120, 121, 122), with an instruction input coupled to an instruction source (10) and a control output coupled to the control input of an execution circuit (124). The instruction decoder (120, 121, 122) comprises a plurality a predecoding circuit (120) with an... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070250687 - Method and apparatus for back to back issue of dependent instructions in an out of order issue queue: A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070250688 - Simd type parallel arithmetic device, processing element and control system of simd type parallel arithmetic device: An SIMD arithmetic processing device having a processing element based on the VLIW system which is capable of simultaneously executing a plurality of instruction streams by one sequencer, which includes a PE array 109 formed of PE based on the k-way VLIW system capable of simultaneously executing instructions to the... Agent: Foley And Lardner LLP Suite 500

20070250689 - Method and apparatus for improving data and computational throughput of a configurable processor extension: Methods and apparatus adapted for enhancing the throughput of a digital processor (e.g., microprocessor, CISC device, or RISC device) through use of a direct memory access (DMA) mechanism. In one embodiment, the processor comprises a “soft” RISC-based processor core that is both user-extensible and user-configurable. The core comprises a functional... Agent: Gazdzinski & Associates

20070245120 - Multiple microcontroller system, instruction, and instruction execution method for the same: In a multiple microcontroller system comprising multiple MCU core logics, a multiple-MCU-core-logic selection operand is provided in an instruction according to this invention. The multiple-MCU-core-logic selection operand specifies or selects a corresponding MCU core logic in the system, and also specifies or selects a sub-unit of the MCU core logic,... Agent: Rosenberg, Klein & Lee

20070245121 - Computer processor array with independent computational functions: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output... Agent: Henneman & Associates, PLC

20070245122 - Executing an allgather operation on a parallel computer: Executing an allgather operation on a parallel computer that includes a plurality of compute nodes where the compute nodes are organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer, and each compute node in the operational group is assigned a unique... Agent: Ibm (roc-blf)

20070245123 - Parallel data processing apparatus: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial... Agent: Glenn Patent Group

20070245124 - Distributed memory type information processing system: In parallel computers, sorting and calculation of large-scale data are realized while large-scale data is held in the respective processors without sharing the large-scale data between the processors so as to reduce the communication between the processors. An information processing method gives global dimension value numbers common to all the... Agent: Griffin & Szipl, PC

20070245125 - Controller and resource management system and method with improved security for independently controlling and managing a computer system: A controller and resource management system and method with improved security for independently controlling and managing a computer system is provided. Control, management and security protection is provided while functioning: conceptually, logically, functionally, operatively, physically and electrically independent of computer system resources, including processors. All computer system resources, including processors... Agent: Cantor Colburn, LLP

20070245126 - Program counter of microcontroller and control method thereof: A program counter of a microcontroller and a method for controlling the same are disclosed. The program counter receives an external input program count indicating an address of a program to be executed by the microcontroller when the microcontroller wakes up out of a power-save/sleep mode, whereby the microcontroller can... Agent: Oliff & Berridge, PLC

20070245128 - Cache metadata for accelerating software transactional memory: Various technologies and techniques are disclosed for providing a hardware accelerated software transactional memory application. The software transactional memory application has access to metadata in a cache of a central processing unit that can be used to improve the operation of the STM system. For example, open read barrier filtering... Agent: Microsoft Corporation

20070245127 - Reconfigurable control structure for cpus and method of operating same: A method is provided for using a reconfigurable control structure that includes a hard-wired control unit configured to execute a pre-defined instruction set and a programmable control unit configured to execute a programmable instruction set. The method includes associating with each of a plurality of instructions to be executed an... Agent: Seed Intellectual Property Law Group PLLC

20070245129 - Issue unit for placing a processor into a gradual slow mode of operation: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070245130 - Parallel data processing apparatus: A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements. The controller is operable to determine respective status information for a plurality of processing threads, and to control processing of the processing threads by the... Agent: Glenn Patent Group

20070245131 - Semiconductor device: A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a control line for receiving a rule signal; a circuit... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070245132 - Parallel data processing apparatus: A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction... Agent: Glenn Patent Group

20070245133 - Method and device for switching between at least two operating modes of a processor unit: A method and a device are described for switching between at least two operating modes of a processor unit including at least two execution units for running programs, at least one identifier being assigned to at least the programs which differentiates between the at least two operating modes, and switching... Agent: Kenyon & Kenyon LLP

20070239963 - Multiprocessor system: A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor... Agent: Bingham Mccutchen LLP

20070239964 - System and method for dynamically reconfigurable computer architecture based on network connected components: A method, system, computer program product, and devices corresponding to a computer architecture, a computer management system, a programming model, and a programming language product for high performance computing, according to the exemplary embodiments.... Agent: Nixon Peabody, LLP

20070239965 - Inter-partition communication: In a many-core processor based system with many logical processing cores and a system memory, configuring the system so that the cores are segregated into a several partitions, each partition having at least one core and an area of the system memory allocated exclusively for the use of programs executing... Agent: Intel Corporation C/o Intellevate, LLC

20070239966 - Self-contained processor subsystem as component for system-on-chip design: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor... Agent: Scully, Scott, Murphy & Presser, P.C.

20070239967 - High-performance risc-dsp: A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seamless transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070239968 - Data processing system having bit exact instructions and methods therefor: A method for operating a data processing system is provided. The method includes providing a first operand stored in a first register, providing a second operand stored in the register, providing a third operand stored in the register. The method further includes executing a first instruction, where executing the first... Agent: Freescale Semiconductor, Inc. Law Department

20070239969 - Program subgraph identification: There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing... Agent: Nixon & Vanderhye, PC

20070239971 - Partial register forwarding for cpus with unequal delay functional units: A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical functional unit supplies its output to a pipeline register. A comparator and multiplexer select a register input... Agent: Texas Instruments Incorporated

20070239970 - Apparatus for cooperative sharing of operand access port of a banked register file: An apparatus for cooperative sharing of operand access port of a banked register file comprises a partitioned register file, a first group of functional unit, a second group of function units and an access control circuit. The access control circuit includes three control bits to control the accesses to the... Agent: Lin & Associates Intellectual Property

20070239972 - Processing internal timestamp counter instructions in reference to external counter: Internal timestamp counter instructions are instead processed in reference to an external counter. A processor receives an instruction to access an internal timestamp counter of the processor, such as from software code containing the instruction that is currently being executed by the processor. The processor processes the instruction, however, in... Agent: Law Offices Of Michael Dryja

20070239973 - Processor and processing method for reusing arbitrary sections of program code: A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular... Agent: Mitch Harris, LLC - Cirrus

20070239974 - System and method for target branch prediction using correlation of local target histories: An information processing system includes a branch target buffer (BTF) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potential branch targets based on a history of the branch and... Agent: Michael J. Buchenhorner

20070239975 - Programmable backward jump instruction prediction mechanism: A programmable backward jump instruction prediction mechanism includes a backward branch prediction queues (BBQ) for assisting an embedded processor to overcome an inevitable control hazard caused in a pipeline execution for a conditional branch instruction. A large percentage of nested loops exists in an application program executed by the embedded... Agent: Rosenberg, Klein & Lee

20070234007 - Electronic data processing device with dual-cpu: The present invention discloses an electronic data processing device with dual-CPU, comprising: the first CPU and the second CPU, wherein the first CPU is connected to the second CPU. The first CPU being low power type executes the first process which needs long time to execute. The second CPU with... Agent: G. Link Co., Ltd.

20070234006 - Integrated circuit and metod for issuing transactions: An integrated circuit is provided comprising a plurality of processing modules (M, S) and a network (N) arranged for coupling said processing modules (M, S). Said integrated circuit comprises a first processing module (M) for encoding an atomic operation into a first transaction and for issuing said first transaction to... Agent: Philips Intellectual Property & Standards

20070234008 - Non-temporal memory reference control mechanism: An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and... Agent: Huffman Law Group, P.C.

20070234009 - Processor having a dedicated hash unit integrated within: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on... Agent: Fish & Richardson, PC

20070234010 - Suppression of store checking: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix... Agent: Huffman Law Group, P.C.

20070234011 - Method and system for on-demand scratch register renaming: A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected registers and a pool of one or more rename registers and allocating... Agent: Dillon & Yudell LLP

20070234012 - Methods and apparatus for dynamic register scratching: Apparatus and methods of reducing dynamic memory stack by a register stack engine are disclosed. An example apparatus and method identifies a local parameter of a caller function. A scratch register corresponding to the local parameter is moved to the top of a register stack, and a local parameter of... Agent: Hanley, Flight & Zimmerman, LLC

20070234013 - Semiconductor device: An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting... Agent: Arent Fox PLLC

20070234014 - Processor apparatus for executing instructions with local slack prediction of instructions and processing method therefor: A processor predicts predicted slack which is a predicted value of local slack of an instruction to be executed and executes the instruction using the predicted slack. A slack table is referred to upon execution of an instruction to obtain predicted slack of the instruction and execution latency is increased... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070234015 - Apparatus and method of providing flexible load and store for multimedia applications: An apparatus and method of providing flexible load and store for multimedia applications are provided by the present invention, which comprising a register file, a load and store unit, a memory, a selective maskable permutable and collector load module (SMPCKM), and a control unit. The load and store unit includes... Agent: Sinorica, LLC

20070234016 - Method and system for trace generation using memory index hashing: A method and system for trace generation using memory index hashing. A method may include generating an extended trace representative of M threads of instruction execution from a trace representative of N threads of instruction execution, where N and M are integers, N≧1 and M>N, and where each of the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070234017 - Selective instruction breakpoint generation: A method includes generating an instruction address value in response to an instruction source event. The method further includes selectively generating a breakpoint request based on the instruction source event and responsive to a comparison of the instruction address value to a breakpoint address value. In one embodiment, selectively generating... Agent: Larson Newman Abel Polansky & White, LLP

20070234018 - Method to detect a stalled instruction stream and serialize micro-operation execution: A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070234019 - Processor apparatus and complex condition processing method: Disclosed is a processor apparatus that has an instruction set that includes a complex conditional branch instruction that performs comparison operations corresponding to one or more conditions and causes a branch to a specified branch destination to be taken, based on a comparison operation between a result of the comparison... Agent: Foley And Lardner LLP Suite 500

20070234020 - Instruction encoding for system register bit set and clear: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a... Agent: Huffman Law Group, P.C.

20070234021 - Inter-port communication in a multi-port memory device: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of... Agent: Perkins Coie LLP Patent-sea