Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 09/07

20070226453 - Method for improving processing of relatively aligned memory references for increased reuse opportunities: Computer implemented method, system and computer program product for aligning vectors to be processed by SIMD code. A pair of vectors to be aligned at runtime and having a known relative alignment at compile time is identified. A modified second memory reference is generated by modifying an address of the... Agent: Duke W. Yee Yee & Associates, P.C.

20070226457 - Computer system with increased operating efficiency: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed... Agent: Henneman & Associates, PLC

20070226454 - Highly scalable mimd machine for java and .net processing: An MIMD processor for Java and Net processing includes a plurality of “half-processors,” separate execution units, and memory caches. Each half-processor is an MIMD processing element having resources for instruction fetch and decode and for instruction stream context management, but excluding execution resources. In other words, the execution resources are... Agent: Mccormick, Paulding & Huber LLP

20070226456 - System and method for employing multiple processors in a computer system: There is provided a system and a method for employing multiple processors in a computer system. More specifically, there is provided a computer system comprising a first cell board including a first central processing unit, a second central processing unit, and a first data agent coupled to the first and... Agent: Hewlett Packard Company

20070226455 - Variable clocked heterogeneous serial array processor: A serial array processor, whose execution unit, which s comprised of a multiplicity of single bit arithmetic logic units (ALUs), performs parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while the instruction unit is pre-fetching the... Agent: Laurence H. Cooke

20070226458 - Parallel data processing apparatus: A data processor comprises a plurality of processing elements arranged in a first plurality of SIMD (single instruction multiple data) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to transfer at least one instruction stream, and to transfer... Agent: Glenn Patent Group

20070226459 - Data gathering/data processing device for video/audio signals: In order to create a data gathering/data processing device for video/audio signals which includes a plurality of signal processors and which has an optimized hardware architecture, it is provided that the signal processors or a subset of the signal processors are coupled to a network having a star-shaped topology.... Agent: Kenyon & Kenyon LLP

20070226460 - Scalable multiple processor computing apparatus which supports secure physical partitioning and heterogeneous programming across operating system partitions: A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job... Agent: Sandia Corporation

20070226461 - Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device: The disclosure relates to a reverse Polish notation processing device making it possible to execute a set of instructions and implementing management of a stack whose size is variable. The device includes a storage device including a random access memory; a device for managing a stack pointer, which is a... Agent: Westman Champlin & Kelly, P.A.

20070226462 - Data processor having dynamic control of instruction prefetch buffer depth and method therefor: A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions.... Agent: Larson Newman Abel Polansky & White, LLP

20070226464 - Patchable and/or programmable pre-decode: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings... Agent: Gunnison Mckay & Hodgson, LLP

20070226463 - Patchable and/or programmable decode using predecode selection: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a... Agent: Gunnison Mckay & Hodgson, LLP

20070226465 - Technique for executing selected instructions in order: A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream... Agent: Gunnison Mckay & Hodgson, LLP

20070226467 - Working register file entries with instruction based lifetime: A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a... Agent: Gunnison Mckay & Hodgson, LLP

20070226466 - Method, system and program product for simd-oriented management of register maps for map-based indirect register-file access: A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed... Agent: Ibm Corporation Department 417

20070226468 - Arrangements for controlling instruction and data flow in a multi-processor environment: In one embodiment a method for controlling instruction flow in a multiprocessor environment is disclosed. The method can include retrieving at least one slice instruction that is executable by more than one processing unit in a plurality of processing units. The method can also retrieve a global instruction that indicates... Agent: Alan Carlson

20070226469 - Permutable address processor and method: Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the... Agent: Iandiorio & Teska

20070226470 - Technique to perform memory disambiguation: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.... Agent: Caven & Aghevli C/o Intellevate

20070226473 - Breakpointing on register access events or i/o port access events: A data processing system 2 is provided with breakpoint circuitry 28 having breakpoint registers 30 which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register 8 or a... Agent: Nixon & Vanderhye, PC

20070226471 - Data processing apparatus: A data processing apparatus, method and watch point unit are disclosed. The data processing apparatus comprises: a processor core operable to process a sequence of instructions; and a watch point unit operable to receive an indication of each of the sequence of instructions being processed by the processor core, the... Agent: Nixon & Vanderhye, PC

20070226472 - Method and apparatus for sampling instructions on a processor that supports speculative execution: One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070226474 - Method and system for providing context switch using multiple register file: A context switch method capable of promptly switching a context for a dynamically generated task and a dynamic link by converting a state of multiple register files, switching the context, and separately restoring and storing the context. That is, the context switch method includes: maintaining a multiple register files; establishing... Agent: Staas & Halsey LLP

20070226475 - Effective elimination of delay slot handling from a front section of a processor pipeline: Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without... Agent: Gunnison Mckay & Hodgson, LLP

20070226476 - Firmware extendable commands for a microcontroller based flash memory digital controller: A system and method for expanding the command set of a memory controller is provided. In one implementation, the method includes decoding a first plurality of commands through a command decoding state machine, and in response to the command decoding state machine decoding an extended command, waking the microcontroller to... Agent: Sawyer Law Group LLP

20070220232 - Data processing architectures: A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in... Agent: Potomac Patent Group, PLLC

20070220234 - Autonomous multi-microcontroller system and the control method thereof: The present invention discloses an autonomous multi-microcontroller system and the control method thereof, wherein any MCU core logic of the multi-microcontroller system can directly place the starting address of an inserted program into the program counter of a controllee MCU core logic. The address of the interrupted program of the... Agent: Rosenberg, Klein & Lee

20070220233 - Common analog interface for multiple processor cores: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate... Agent: Trop Pruner & Hu, PC

20070220235 - Instruction subgraph identification for a configurable accelerator: An integrated circuit 2 includes a configurable accelerator 14. An instruction identifier 22 identifies subgraphs of program instructions which are capable of being performed as combined complex operations by the configurable accelerator 14. The subgraph identifier 22 reorders the sequence of fetched instructions to enable larger subgraphs of program instructions... Agent: Nixon & Vanderhye, PC

20070220236 - Reconfigurable computing device: A reconfigurable computing device includes computing unit groups each of which includes at least one computing unit; a bus network that is reconfigurable and that uses arbitrary output data of the computing unit groups as arbitrary input data for the computing unit groups; a sequencer that outputs address information for... Agent: Staas & Halsey LLP

20070220237 - Method and apparatus for analyzing performance, and computer product: In a performance analyzing apparatus, a setting unit sets an event of which the performance is desired to be monitored, a detecting unit detects an instruction address at the time of generation of an interrupt signal from a timer, and a calculating unit calculates a variation amount of a counted... Agent: Staas & Halsey LLP

20070220238 - Dynamic readjustment and interpolation of progress method and system: A method for readjusting and interpolating a progress of an execution of multi-step program by a computing device involves a computation of a cumulative point baseline for each step of the multi-step program based on a completion time baseline for each step of the multi-step program, and a regulation of... Agent: Cardinal Law Group

20070220239 - Representing loop branches in a branch history register with multiple bits: In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored... Agent: Qualcomm Incorporated

20070220240 - Method and apparatus for micro-code execution: A method for micro-code execution for an electronic device is disclosed. The method includes: providing the electronic device with a micro-code partitioned into a main core and at least a function code, the micro-code being stored in a first storage module of the electronic device; and when the electronic device... Agent: North America Intellectual Property Corporation

20070214341 - Data processing system with trace co-processor: The present invention relates to a processing device and a tracing system and method for providing to an external debugging device a trace information relating to an application program. A trace processor (40) is provided in order to relieve a main processor (10) of tasks relating to tracing. The main... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070214342 - System to profile and optimize user software in a managed run-time environment: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant... Agent: Blakely Sokoloff Taylor & Zafman

20070214343 - Across-thread out-of-order instruction dispatch in a multithreaded microprocessor: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution,... Agent: Townsend And Townsend And Crew LLP

20070208922 - Information processing apparatus: An information processing apparatus includes: a device group including a device which processes information and a device which stores information; and a switch which is connectable to a plurality of devices selected from the device group, and which allows information to be exchanged between devices connected to the switch.... Agent: Young & Thompson

20070208923 - Array element mesh system devices for medical, maintenance, and other small form factor applications: Disclosed is an ultraminiaturized Auto-Locomotive Device (ALD) apparatus with tool actuators and traction, locomotion, and propulsion mechanisms. The ALD is capable of static and dynamic activity, including moving to a target work area or structure, stopping, turning, anchoring, operating ALD actuator tools, auxiliary peripherals, etc., in response to external tactical... Agent: David Russell

20070208924 - Handling of conditional instructions in a data processing apparatus: A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of... Agent: Nixon & Vanderhye, PC

20070208925 - Device and method for rendering data: A method and an electronic device (1) for rendering a main sequence of digital data and a sub sequence of digital data being associated with the main sequence. In response to activating a certain key of a keypad (10) of the electronic device (1), execution of the main sequence is... Agent: Harrity Snyder, L.L.P.