Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 08/07

20070204131 - Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations... Agent: Hogan & Hartson LLP

20070204132 - Storing and processing simd saturation history flags and data size: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed... Agent: Oliff & Berridge, PLC

20070204133 - Information processing device, compressed program producing method, and information processing system: An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the output from the instruction buffer; an instruction decompression section for decompressing the output from the first selector into an original instruction;... Agent: Mcdermott Will & Emery LLP

20070204134 - Instruction sets for microprocessors: A method and apparatus are provided for selecting between a plurality of instruction sets available to a microprocessor. An instruction fetch address is supplied. At least one predetermined bit of the instruction fetch address is used to select between the instruction sets. Once an instruction set has been selected instructions... Agent: Flynn Thiel Boutell & Tanis, P.C.

20070204136 - Reordering apparatus: A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column numbers correspond to positions within the order of the entries, and every matrix element corresponding to the storage position and the position within the order of the... Agent: Staas & Halsey LLP

20070204135 - Distributive scoreboard scheduling in an out-of order processor: A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070204137 - Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0,... Agent: Texas Instruments Incorporated

20070204138 - Device, system and method of tracking data validity: Devices, systems and methods of tracking data validity. For example, a method includes determining whether a condition related to validity of data in a reorder buffer of an out-of-order subsystem of a processor core is met, based on a criterion other than a valid data indication from said reorder buffer.... Agent: Pearl Cohen Zedek Latzer, LLP

20070204139 - Compact linked-list-based multi-threaded instruction graduation buffer: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070204140 - Integrated circuit with memory and method of configuring a memory: An integrated circuit (10) comprises a processor (12) configured for fetching and executing opcodes, a system bus (14), and a memory (16) coupled to the processor via the system bus. The memory includes logic circuitry (26) for detecting functional states of the memory, wherein the memory (a) supplies one or... Agent: Freescale Semiconductor, Inc. Law Department

20070204141 - Recording medium, data management method, and program: The invention provides a removable medium capable of suitably managing digital images, music, and/or data with a specified use rule. An SD card is insertable into/removable from plural host apparatuses and includes digital data recorded therein. The SD card includes an expiration date determination processing unit for determining whether or... Agent: Greenblum & Bernstein, P.L.C

20070204142 - Method and apparatus for repairing a link stack: A link stack in a processor is repaired in response to a procedure return address misprediction error. In one example, a link stack for use in a processor is repaired by detecting an error in a procedure return address value retrieved from the link stack and skipping a procedure return... Agent: Qualcomm Incorporated

20070198808 - Processor pipeline architecture logic state retention systems and methods: A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of... Agent: Hoffman, Warnick & D'alessandro LLC

20070198809 - Method and apparatus for increasing the efficiency of an emulation engine: A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20070198810 - Cpu datapipe architecture with crosspoint switch: Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality... Agent: Lathrop & Gage Lc

20070198811 - Data-driven information processor performing operations between data sets included in data packet: A data pair detector queues data to be paired, generates a data packet including the data to be paired, and outputs the data packet. An operation unit selects the data which are subject to an operation from a first data set included in the data packet outputted from the data... Agent: Birch Stewart Kolasch & Birch

20070198812 - Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system: An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array... Agent: Mark P. Kahler

20070198813 - Synchronized register renaming in a multiprocessor: Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in the processors. An ideal and an external register allocation map are implemented in the coprocessor. When registers are no longer allocated according to the... Agent: Macpherson Kwok Chen & Heid LLP

20070198814 - Method and apparatus for distributing flush instructions: A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070198815 - Programmable digital signal processor having a clustered simd microarchitecture including a complex short multiplier and an independent vector load unit: A programmable digital signal processor with a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core, and a complex computing unit. Each of the accelerator units may perform one or more dedicated functions. The processor core includes an integer execution unit that may execute integer instructions. The... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070198816 - Emulation system for a single-chip multiple-microcontroller and emulation method thereof: The present invention discloses an emulation system for a single-chip multiple-microcontroller and an emulation method thereof, wherein a multiple-microcontroller emulator comprises: an emulation control logic, at least two microcontrollers, and program counters separately related to the microcontrollers; each program counter corresponds to at least one breakpoint address; every executing program... Agent: Rosenberg, Klein & Lee

20070198817 - Microprocessor and processing method thereof: A microprocessor a microprocessor includes: a processor module executing an instruction to generate trace information including the information of the kind and the length of the instruction; an application processing circuit operating in cooperation with the processor module to process a specific application; an address calculating circuit calculating an execution... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070192567 - Configurable co-processor interface: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the... Agent: Huffman Law Group, P.C.

20070192566 - Method and apparatus for monitoring inputs to a computer: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC

20070192565 - Semiconductor device and mobile phone using the same: A semiconductor device (100) comprises a processor unit (110) including an internal CPU (113), an internal interface section (130), an external interface section (140) including an interface unit (143) connected to an external CPU (201), a plurality of processing circuits (121)-(126), and a connection control circuit (180). The internal interface... Agent: Wenderoth, Lind & Ponack L.L.P.

20070192568 - Thread optimized multiprocessor architecture: In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein... Agent: Morgan Lewis & Bockius LLP

20070192569 - Reverse polish notation processing device, and electronic integrated circuit including such a processing device: The disclosure relates to a reverse Polish notation processing device, allowing execution of a set of instructions wherein each instruction comprises N operands at most, where N≧1. The device implements management of a stack whose size is variable. Such a device includes: a storage device including a random access memory... Agent: Westman Champlin & Kelly, P.A.

20070192570 - Execution of instructions directly from input source: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC

20070192571 - Programmable processing unit providing concurrent datapath operation of multiple instructions: In general, in one aspect, the disclosure describes a processing unit that includes a datapath having an input buffer, at least one memory, and an arithmetic logic unit, and control logic having access to a program instruction control store. The control logic controls operation of the datapath and may concurrently... Agent: Blakely Sokoloff Taylor & Zafman

20070192572 - Minimum processor instruction for implementing weighted fair queuing and other priority queuing: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present... Agent: Thomas, Kayden, Horstemeyer & Risley, L.L.P.

20070192573 - Device, system and method of handling fxch instructions: Some embodiments of the invention provide devices, systems and methods of handling FXCH instructions data validity. For example, an apparatus in accordance with an embodiment of the invention includes a real register file unit able to perform a floating point exchange micro-instruction, by modifying an operand of a floating point... Agent: Pearl Cohen Zedek Latzer, LLP

20070192574 - Branch target buffer, a branch prediction circuit and method thereof: A branch target buffer, a branch prediction circuit and a method thereof are provided. The example branch target buffer may include a memory cell array storing a branch address and a target address, a decoder connected to the memory cell array through a word line, and providing a word line... Agent: Harness, Dickey & Pierce, P.L.C

20070192575 - Microloop computer instructions: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready... Agent: Henneman & Associates, PLC

20070192576 - Circular register arrays of a computer: A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern.... Agent: Henneman & Associates, PLC

20070186076 - Data pipeline transport system: A series of pipeline stages are interconnected with other similar stages in arbitrary topologies. Data travel is controlled and regulated by forward and back-pressure mechanisms.... Agent: Ambric, Inc. C/o Marger Johnson & Mccollom PC

20070186077 - System and method for executing instructions utilizing a preferred slot alignment mechanism: A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070186078 - Integrated circuit device: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit,... Agent: Marshall, Gerstein & Borun LLP

20070186079 - Digital signal processor with variable length instruction set: A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction... Agent: Qualcomm Incorporated

20070186080 - Mechanism to minimize unscheduled d-cache miss pipeline stalls: A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070186081 - Supporting out-of-order issue in an execute-ahead processor: One embodiment of the present invention provides a system which supports out-of-order issue in a processor that normally executes instructions in-order. The system starts by issuing instructions from an issue queue in program order during a normal-execution mode. While issuing the instructions, the system determines if any instruction in the... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070186082 - Stream processor with variable single instruction multiple data (simd) factor and common special function: Included are embodiments of a stream processor configured to process data in any of a plurality of different formats. At least one embodiment of the stream processor includes a first scalar arithmetic logic unit (ALU), configured to process a plurality of sets of short data in response to a received... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070186084 - Circuit and method for loop control: A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction,... Agent: Foley And Lardner LLP Suite 500

20070186083 - Pipelined processor and instruction loop execution method: Processor (10) having a processing pipeline (100) is extended with an arrangement to reduce the loss of cycles associated with loop execution in pipeline (100). Loop start detection until (116a) detects a loop start instruction containing information about the loop count and last instruction in the loop information about the... Agent: Meredith & Keyhani, PLLC

20070186085 - Method, medium, and apparatus with interrupt handling in a reconfigurable array: A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is... Agent: Staas & Halsey LLP

20070180220 - Processor system: A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a... Agent: Sughrue Mion, PLLC

20070180221 - Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines: An apparatus and method for handling data cache misses out-of-order for asynchronous pipelines are provided. The apparatus and method associates load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.