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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) July cataloged USPTO category listing 07/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/26/2007 > patent applications in patent subcategories. cataloged USPTO category listing
20070174587 - Address space emulation: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20070174586 - Processor controlled interface: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment... Agent: Rambus Lerner, David, Et Al.
20070174588 - Processes and devices for compression and decompression of executable code by a microprocessor with risc architecture: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words... Agent: Graybeal Jackson Haley LLP
20070174589 - Processor having inactive state of operation and method thereof: Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set... Agent: Pearl Cohen Zedek Latzer, LLP
20070174590 - Run-time selection of feed-back connections in a multiple-instruction word processor: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and... Agent: Philips Intellectual Property & Standards
20070174592 - Early conditional selection of an operand: Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made... Agent: Qualcomm Incorporated
20070174593 - Managing and enhancing execution over parallel pipelines: A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks (are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation... Agent: Xilinx, Inc Attn: Legal Department
20070174591 - Processing device: A transaction input/output CPU receives a transaction to be processed and outputs the execution result of the transaction. A plurality of processing CPUs execute the transaction according to an instruction from the transaction input/output CPU. A plurality of memory areas are related to each processing CPU and store a transaction... Agent: Staas & Halsey LLP
20070174594 - Processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20070174595 - Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20070174596 - Data processor: A data processor, and particularly in a data processor performing condition execution on the basis of flag information, aims at obtaining a data processor having excellent code efficiency, which can reduce branch penalty. In order to attain the aforementioned object, it is so structured that, when a first instruction decoded... Agent: Buchanan, Ingersoll & Rooney PC
20070174597 - Multiple-thread processor with in-pipeline, thread selectable storage: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline.... Agent: Gunnison Mckay & Hodgson, LLP
20070174598 - Processor having a data mover engine that associates register addresses with memory addresses: A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20070174599 - Method and apparatus for high performance branching in pipelined microsystems: A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and multiply pipelined machines, branches can potentially cause the pipeline to stall because the branch alters... Agent: Fletcher Yoder (micron Technology, Inc.)07/19/2007 > patent applications in patent subcategories. cataloged USPTO category listing
20070168645 - Methods and arrangements for conditional execution of instructions in parallel processing environment: Methods and processor architectures for the execution of instruction having a condition are disclosed. Very long instruction words can be loaded from a memory unit into an instruction word decoder and the decoder can separate the VLIW into processable sequences. Each processable sequence can be processable by a processing unit... Agent: Alan Carlson
20070168647 - System and method for acceleration of streams of dependent instructions within a microprocessor: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20070168646 - Data exchange between cooperating processors: One embodiment relates to a computer apparatus including at least a microprocessor having an address space, an accelerator configured to cooperatively execute a program with the microprocessor, and a data register in the accelerator. The data register in the accelerator is mapped into the memory address space of the microprocessor.... Agent: Hewlett Packard Company
20070168648 - Modular computing system: The present invention discloses systems and methods for a computing portal system including: a computing engine for performing computing operations; at least one memory component for storing program code of an operating system; a computing-engine connector for providing operational connectivity to the engine, wherein the connector is a contact pad;... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn
20070168649 - Control of priority and instruction rates on a multithreaded processor: A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored and requests are issued to cause instructions to execute in response to the... Agent: Flynn Thiel Boutell & Tanis, P.C.
20070168650 - Sharing a data buffer: A method of executing program instructions may include receiving, in a processor, an instruction that causes the processor to read data from or write data to a portion of memory that is shared by one or more processes, at least one process of which manipulates data in a format that... Agent: Fish & Richardson P.C.
20070168651 - Method and apparatus for debugging a multicore system: Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating... Agent: Qualcomm Incorporated07/12/2007 > patent applications in patent subcategories. cataloged USPTO category listing
20070162722 - Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems: An efficient method and device for the parallel processing of data variables. A parallel processing array has computing elements configured to process data variables in parallel. An algorithm for a plurality of computing elements of a parallel processor is loaded. The algorithm includes a plurality of processing steps. Each of... Agent: Dla Piper Rudnick Gray Cary Us, LLP
20070162723 - Technique for reducing traffic in an instruction fetch unit of a chip multiprocessor: A processor includes a fetch pipeline, out-of-order (OOO) logic and a strand selector. The fetch pipeline is configured to provide instructions from an instruction store to a fetch buffer responsive to receiving a plurality of fetch requests for a first strand, selected from a plurality of active strands. The OOO... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP
20070162724 - Memory-efficient instruction processing scheme: In a two-dimensional optical storage (TwoDOS) arrangement, at certain places on the optical disc, calibration pits are placed, for instance in the lead-in and/or additionally sparsely in the data. The signal waveform resulting from the read out of the calibration bits is measured, and matrix multiplication is performed on these... Agent: Philips Electronics North America Corporation Intellectual Property & Standards
20070162726 - Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit: Methods and apparatus are provided for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit. A method for executing instructions in a processor having a polymorphic execution unit includes the steps of reloading a state associated with a first instruction class and reconfiguring... Agent: Keusey, Tutunjian & Bitetto, P.C.
20070162725 - Method and related device for use in decoding executable code: The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling code at run-time, and including the steps of dividing the code into a plurality of sub-portions, identifying sub-portions of the code... Agent: Philips Electronics North America Corporation Intellectual Property & Standards
20070162727 - Reconfigurable processor and apparatus: Provided is a reconfigurable processor or apparatus capable of changing a logic without any loss of input data and without any deterioration of data computing processing performance, which is impossible with a conventional reconfigurable processor or apparatus. The processor or apparatus is realized by a system for distributing only data... Agent: Stanley P. Fisher Reed Smith LLP
20070162728 - Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative... Agent: Staas & Halsey LLP
20070162729 - Method and apparatus for interrupt handling in coarse grained array: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse... Agent: Sughrue Mion, PLLC07/05/2007 > patent applications in patent subcategories. cataloged USPTO category listing
20070157004 - Multi purpose switching circuit and electronic apparatus including same: A multi purpose switching circuit is provided. The multi purpose switching circuit is connected with a main unit (60) of an electronic apparatus and includes a multi purpose switch (10). The multi purpose switch is capable of receiving multiple manual operational inputs and accordingly producing multiple command signals. The multiple... Agent: North America Intellectual Property Corporation
20070157005 - Copy program and recording medium in which the copy program is recorded: This invention provides a copy program by which the data such as static image data or moving image data, music data, can be successively copied in a recording means such as a recording medium, by a simple operation, and the recording medium in which the copy program is recorded. The... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20070157006 - Method and apparatus for microarchitecture partitioning of execution clusters: Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To... Agent: Intel Corporation C/o Intellevate, LLC
20070157007 - Forward-pass dead instruction identification: Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead... Agent: Intel Corporation C/o Intellevate, LLC
20070157008 - Microarchitecture prediction of execution clusters and inter-cluster communications: Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations.... Agent: Intel Corporation C/o Intellevate, LLC
20070157009 - Loop accelerator and data processing system having the same: Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file... Agent: Sughrue Mion, PLLCPrevious industry: Electrical computers and digital processing systems: memory
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