Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions 06/07

20070150697 - Vector processor with multi-pipe vector block matching: A vector processor includes a set of vector registers for storing data to be used in the execution of instructions and a vector functional unit coupled to the vector registers for executing instructions. The functional unit executes instructions using operation codes provided to it which operation codes include a field... Agent: Townsend And Townsend And Crew, LLP

20070150698 - Manifold array processor: An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data... Agent: Priest & Goldstein PLLC

20070150699 - Firm partitioning in a system with a point-to-point interconnect: Methods and apparatuses for firm partitioning of a computing platform.... Agent: Blakely Sokoloff Taylor & Zafman

20070150700 - System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values: A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due... Agent: Crawford Maunu PLLC

20070150701 - Method and arrangement for power-efficient control of processors: A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied... Agent: Baker Botts L.L.P.

20070150702 - Processor: A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor... Agent: Fenwick & West LLP

20070150703 - Breaking a lock situation in a system: In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In... Agent: Trop Pruner & Hu, PC

20070150704 - Data processor: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by... Agent: Mcdermott Will & Emery LLP

20070150705 - Efficient counting for iterative instructions: Methods and apparatus to provide efficient counting of the number of retired iterations of an iterative instruction are described. In one embodiment, the number of retired iterations of an iterative instruction is determined.... Agent: Caven & Aghevli C/o Intellevate

20070150706 - Reducing data hazards in pipelined processors to provide high processor utilization: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070150707 - Processor and pipeline reconfiguration control method: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it... Agent: Staas & Halsey LLP

20070150708 - System, method and storage medium for controlling asynchronous updates to a register: A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070150709 - Method and system for state tracking and recovery in multiprocessing computing systems: Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to be recovered. This eliminates... Agent: Scully Scott Murphy & Presser, PC

20070150710 - Apparatus and method for optimizing loop buffer in reconfigurable processor: A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a... Agent: Sughrue Mion, PLLC

20070150711 - Apparatus and method of exception handling for reconfigurable architecture: A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first... Agent: Sughrue Mion, PLLC

20070150712 - Deferred branch history update scheme: In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070143575 - Flow optimization and prediction for vsse memory operations: In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and... Agent: Blakely Sokoloff Taylor & Zafman

20070143574 - Method and apparatus for supporting vector operations on a multi-threaded microprocessor: One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070143576 - Apparatus and method for performing signal processing: A system for performing signal processing includes a system input, wherein a first signal having a first format, and supplied on a first system input is selected by a user for format conversion. A switching circuit having plural switching circuit inputs and plural switching circuit outputs is provided for routing... Agent: Buchanan, Ingersoll & Rooney PC

20070143577 - Reconfigurable integrated circuit: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated... Agent: Dennison, Schultz & Macdonald

20070143578 - System and method for message passing fabric in a modular processor architecture: The invention provides a system and method of providing a message passing fabric in a modular processing system where a plurality of processing elements (VFBs), access other available processing elements to provide a message passing fabric where the fabric asynchronously establishes routes for synchronous messages from an origin processing element... Agent: Robert S. Lipton, Esquire

20070143579 - Integrated data processor: An integrated data processor of the present invention integrates a plurality of functions of a digital signal processor (DSP) and a microprocessor control unit (MCU). A plurality of novel instructions and pipeline parallelism architecture are applied. A pipeline parallelism intends to have read/write actions executed in different stages, so as... Agent: Bacon & Thomas, PLLC

20070143580 - Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors: In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the... Agent: Huffman Law Group, P.C.

20070143581 - Superscalar data processing apparatus and method: A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines... Agent: Nixon & Vanderhye, PC

20070143582 - System and method for grouping execution threads: Multiple threads are divided into buddy groups of two or more threads, so that each thread has assigned to it one or more buddy threads. Only one thread in each buddy group actively executes instructions and this allows buddy threads to share hardware resources, such as registers. When an active... Agent: Patterson & Sheridan, L.L.P.

20070136559 - Method and system of communicating between peer processors in soc environment: A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one... Agent: Greenblum & Bernstein, P.L.C

20070136560 - Method and apparatus for a shift register based interconnection for a massively parallel processor array: A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transfer data between PEs in the MPP... Agent: Dickstein Shapiro LLP

20070136561 - Systems, methods, and computer program products for packing instructions into register files: Embodiments of the present invention may provide for architectural and compiler approaches to optimizing processors by packing instructions into instruction register files. The approaches may include providing at least one instruction register file, identifying a plurality of frequently-used instructions, and storing at least a portion of the identified frequently-used instructions... Agent: Sutherland Asbill & Brennan LLP

20070136562 - Decoupling register bypassing from pipeline depth: One embodiment of the present invention provides a system which decouples register bypassing from pipeline depth. The system starts by storing an intermediate result generated by an originating instruction to an allocated location in an architectural-commit first-in-first-out (ACFIFO) structure and to an allocated location in a working register file (WRF).... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070136563 - Programming methods for a nonvolatile memory device using a y-scan operation during a verify read operation: Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation... Agent: Myers Bigel Sibley & Sajovec

20070136564 - Method and apparatus to save and restore context using scan cells: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070136565 - Stack underflow debug with sticky base: A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack pointer base register. During a course of execution in a single context, the stack pointer base... Agent: Schneck & Schneck

20070130443 - System and method for dynamic selection of services: Example implementations relate to a system for selecting a provider service that fulfills a specification of a service request. The system includes a storage unit, a transformer unit, and a selection unit. The storage unit is configured to store a generic contract that is a concept of an ontology and... Agent: Brake Hughes Bellermann LLP

20070130444 - Integrated processor array, instruction sequencer and i/o controller: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070130445 - Heterogeneous multi-core processor having dedicated connections between processor cores: In general, in one aspect, the disclosure describes dedicated, unidirectional connections between processor cores of a processor featuring heterogeneous processor cores.... Agent: Blakely Sokoloff Taylor & Zafman

20070130446 - Processor apparatus including specific signal processor core capable of dynamically scheduling tasks and its task control method: In a processor apparatus, at least one general purpose central processing unit loads object codes of requested newly-dispatched tasks to a memory. At least one specific signal processing unit core downloads the object codes of the newly-dispatched tasks from the memory to dynamically schedule generation and extinction of the newly-dispatched... Agent: Young & Thompson

20070130447 - System and method for processing thread groups in a simd architecture: A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data processing side and by providing multiple execution pipelines,... Agent: Patterson & Sheridan, L.L.P.

20070130448 - Stack tracker: Methods and apparatus to identify memory communications are described. In one embodiment, an access to a stack pointer is monitored, e.g., to maintain a stack tracker structure. The information stored in the stack tracker structure may be utilized to generate a distance value corresponding to a relative distance between a... Agent: Caven & Aghevli C/o Intellevate

20070130449 - Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement: A processing arrangement (1) includes a processing unit (3) adapted to execute a predetermined set of processing instructions received from an instruction input (12). The set of processing instructions includes at least one predetermined processing instruction adapted to initiate a fixing operation. A memory unit (2) with a multiplicity of... Agent: Slater & Matsil LLP

20070130450 - Unnecessary dynamic branch prediction elimination method for low-power: A system and method for unnecessary dynamic branch prediction elimination in a processor with a dynamic branch predictor, includes a branch distance generation module for generating a branch distance between two consecutive branch instructions, a branch distance table for storing the branch distance generated by the branch distance generation module,... Agent: Birch Stewart Kolasch & Birch

20070130451 - Mechanism for hardware tracking of return address after tail call elimination of return-type instruction: A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining... Agent: Sun Microsystems, Inc. Attn: Timothy Schulte